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[mips] Refactor instructions which move data from or to coprocessors.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171510 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Akira Hatanaka 2013-01-04 19:13:49 +00:00
parent 648c093b2b
commit 5f560bb2eb
3 changed files with 34 additions and 33 deletions
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32
lib/Target/Mips/Mips64InstrInfo.td
View File

@ -308,22 +308,22 @@ def : InstAlias<"move $dst,$src", (DADD CPU64Regs:$dst,CPU64Regs:$src,ZERO_64)>;
/// Move between CPU and coprocessor registers
let DecoderNamespace = "Mips64" in {
def MFC0_3OP64 : MFC3OP<0x10, 0, (outs CPU64Regs:$rt),
(ins CPU64Regs:$rd, uimm16:$sel),"mfc0\t$rt, $rd, $sel">;
def MTC0_3OP64 : MFC3OP<0x10, 4, (outs CPU64Regs:$rd, uimm16:$sel),
(ins CPU64Regs:$rt),"mtc0\t$rt, $rd, $sel">;
def MFC2_3OP64 : MFC3OP<0x12, 0, (outs CPU64Regs:$rt),
(ins CPU64Regs:$rd, uimm16:$sel),"mfc2\t$rt, $rd, $sel">;
def MTC2_3OP64 : MFC3OP<0x12, 4, (outs CPU64Regs:$rd, uimm16:$sel),
(ins CPU64Regs:$rt),"mtc2\t$rt, $rd, $sel">;
def DMFC0_3OP64 : MFC3OP<0x10, 1, (outs CPU64Regs:$rt),
(ins CPU64Regs:$rd, uimm16:$sel),"dmfc0\t$rt, $rd, $sel">;
def DMTC0_3OP64 : MFC3OP<0x10, 5, (outs CPU64Regs:$rd, uimm16:$sel),
(ins CPU64Regs:$rt),"dmtc0\t$rt, $rd, $sel">;
def DMFC2_3OP64 : MFC3OP<0x12, 1, (outs CPU64Regs:$rt),
(ins CPU64Regs:$rd, uimm16:$sel),"dmfc2\t$rt, $rd, $sel">;
def DMTC2_3OP64 : MFC3OP<0x12, 5, (outs CPU64Regs:$rd, uimm16:$sel),
(ins CPU64Regs:$rt),"dmtc2\t$rt, $rd, $sel">;
def MFC0_3OP64 : MFC3OP<(outs CPU64Regs:$rt), (ins CPU64Regs:$rd, uimm16:$sel),
"mfc0\t$rt, $rd, $sel">, MFC3OP_FM<0x10, 0>;
def MTC0_3OP64 : MFC3OP<(outs CPU64Regs:$rd, uimm16:$sel), (ins CPU64Regs:$rt),
"mtc0\t$rt, $rd, $sel">, MFC3OP_FM<0x10, 4>;
def MFC2_3OP64 : MFC3OP<(outs CPU64Regs:$rt), (ins CPU64Regs:$rd, uimm16:$sel),
"mfc2\t$rt, $rd, $sel">, MFC3OP_FM<0x12, 0>;
def MTC2_3OP64 : MFC3OP<(outs CPU64Regs:$rd, uimm16:$sel), (ins CPU64Regs:$rt),
"mtc2\t$rt, $rd, $sel">, MFC3OP_FM<0x12, 4>;
def DMFC0_3OP64 : MFC3OP<(outs CPU64Regs:$rt), (ins CPU64Regs:$rd, uimm16:$sel),
"dmfc0\t$rt, $rd, $sel">, MFC3OP_FM<0x10, 1>;
def DMTC0_3OP64 : MFC3OP<(outs CPU64Regs:$rd, uimm16:$sel), (ins CPU64Regs:$rt),
"dmtc0\t$rt, $rd, $sel">, MFC3OP_FM<0x10, 5>;
def DMFC2_3OP64 : MFC3OP<(outs CPU64Regs:$rt), (ins CPU64Regs:$rd, uimm16:$sel),
"dmfc2\t$rt, $rd, $sel">, MFC3OP_FM<0x12, 1>;
def DMTC2_3OP64 : MFC3OP<(outs CPU64Regs:$rd, uimm16:$sel), (ins CPU64Regs:$rt),
"dmtc2\t$rt, $rd, $sel">, MFC3OP_FM<0x12, 5>;
}
// Two operand (implicit 0 selector) versions:
def : InstAlias<"mfc0 $rt, $rd", (MFC0_3OP64 CPU64Regs:$rt, CPU64Regs:$rd, 0)>;

8
lib/Target/Mips/MipsInstrFormats.td
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@ -176,17 +176,15 @@ class FJ<bits<6> op>
//===----------------------------------------------------------------------===//
// MFC instruction class in Mips : <|op|mf|rt|rd|0000000|sel|>
//===----------------------------------------------------------------------===//
class MFC3OP<bits<6> op, bits<5> _mfmt, dag outs, dag ins, string asmstr>:
InstSE<outs, ins, asmstr, [], NoItinerary, FrmFR>
class MFC3OP_FM<bits<6> op, bits<5> mfmt>
{
bits<5> mfmt;
bits<5> rt;
bits<5> rd;
bits<3> sel;
let Opcode = op;
let mfmt = _mfmt;
bits<32> Inst;
let Inst{31-26} = op;
let Inst{25-21} = mfmt;
let Inst{20-16} = rt;
let Inst{15-11} = rd;

27
lib/Target/Mips/MipsInstrInfo.td
View File

@ -710,6 +710,9 @@ class SCBase<string opstr, RegisterClass RC, Operand Mem> :
let Constraints = "$rt = $dst";
}
class MFC3OP<dag outs, dag ins, string asmstr> :
InstSE<outs, ins, asmstr, [], NoItinerary, FrmFR>;
//===----------------------------------------------------------------------===//
// Pseudo instructions
//===----------------------------------------------------------------------===//
@ -897,21 +900,17 @@ def EXT : ExtBase<"ext", CPURegs>, EXT_FM<0>;
def INS : InsBase<"ins", CPURegs>, EXT_FM<4>;
/// Move Control Registers From/To CPU Registers
def MFC0_3OP : MFC3OP<0x10, 0, (outs CPURegs:$rt),
(ins CPURegs:$rd, uimm16:$sel),"mfc0\t$rt, $rd, $sel">;
def : InstAlias<"mfc0 $rt, $rd", (MFC0_3OP CPURegs:$rt, CPURegs:$rd, 0)>;
def MFC0_3OP : MFC3OP<(outs CPURegs:$rt), (ins CPURegs:$rd, uimm16:$sel),
"mfc0\t$rt, $rd, $sel">, MFC3OP_FM<0x10, 0>;
def MTC0_3OP : MFC3OP<0x10, 4, (outs CPURegs:$rd, uimm16:$sel),
(ins CPURegs:$rt),"mtc0\t$rt, $rd, $sel">;
def : InstAlias<"mtc0 $rt, $rd", (MTC0_3OP CPURegs:$rd, 0, CPURegs:$rt)>;
def MTC0_3OP : MFC3OP<(outs CPURegs:$rd, uimm16:$sel), (ins CPURegs:$rt),
"mtc0\t$rt, $rd, $sel">, MFC3OP_FM<0x10, 4>;
def MFC2_3OP : MFC3OP<0x12, 0, (outs CPURegs:$rt),
(ins CPURegs:$rd, uimm16:$sel),"mfc2\t$rt, $rd, $sel">;
def : InstAlias<"mfc2 $rt, $rd", (MFC2_3OP CPURegs:$rt, CPURegs:$rd, 0)>;
def MFC2_3OP : MFC3OP<(outs CPURegs:$rt), (ins CPURegs:$rd, uimm16:$sel),
"mfc2\t$rt, $rd, $sel">, MFC3OP_FM<0x12, 0>;
def MTC2_3OP : MFC3OP<0x12, 4, (outs CPURegs:$rd, uimm16:$sel),
(ins CPURegs:$rt),"mtc2\t$rt, $rd, $sel">;
def : InstAlias<"mtc2 $rt, $rd", (MTC2_3OP CPURegs:$rd, 0, CPURegs:$rt)>;
def MTC2_3OP : MFC3OP<(outs CPURegs:$rd, uimm16:$sel), (ins CPURegs:$rt),
"mtc2\t$rt, $rd, $sel">, MFC3OP_FM<0x12, 4>;
//===----------------------------------------------------------------------===//
// Instruction aliases
@ -932,6 +931,10 @@ def : InstAlias<"slt $rs,$rt,$imm",
(SLTi CPURegs:$rs,CPURegs:$rt,simm16:$imm)>;
def : InstAlias<"xor $rs,$rt,$imm",
(XORi CPURegs:$rs,CPURegs:$rt,simm16:$imm)>;
def : InstAlias<"mfc0 $rt, $rd", (MFC0_3OP CPURegs:$rt, CPURegs:$rd, 0)>;
def : InstAlias<"mtc0 $rt, $rd", (MTC0_3OP CPURegs:$rd, 0, CPURegs:$rt)>;
def : InstAlias<"mfc2 $rt, $rd", (MFC2_3OP CPURegs:$rt, CPURegs:$rd, 0)>;
def : InstAlias<"mtc2 $rt, $rd", (MTC2_3OP CPURegs:$rd, 0, CPURegs:$rt)>;
//===----------------------------------------------------------------------===//
// Assembler Pseudo Instructions