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PPC64 passes arguments of integral type in i64 registers, not i32. Reflect this

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by promoting smaller integral values (i32 at this point) to i64, then truncating
to get the wanted size.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48030 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bill Wendling 2008-03-07 20:49:02 +00:00
parent 9ed06db5c8
commit 5f5bf3a3fd
1 changed files with 43 additions and 26 deletions
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23
lib/Target/PowerPC/PPCISelLowering.cpp
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@ -1296,7 +1296,8 @@ static const unsigned *GetFPR(const PPCSubtarget &Subtarget) {
return FPR; return FPR;
} }
SDOperand PPCTargetLowering::LowerFORMAL_ARGUMENTS(SDOperand Op, SDOperand
PPCTargetLowering::LowerFORMAL_ARGUMENTS(SDOperand Op,
SelectionDAG &DAG, SelectionDAG &DAG,
int &VarArgsFrameIndex, int &VarArgsFrameIndex,
int &VarArgsStackOffset, int &VarArgsStackOffset,
@ -1408,8 +1409,10 @@ SDOperand PPCTargetLowering::LowerFORMAL_ARGUMENTS(SDOperand Op,
switch (ObjectVT) { switch (ObjectVT) {
default: assert(0 && "Unhandled argument type!"); default: assert(0 && "Unhandled argument type!");
case MVT::i32: case MVT::i32:
if (!isPPC64) {
// Double word align in ELF // Double word align in ELF
if (Expand && isELF32_ABI) GPR_idx += (GPR_idx % 2); if (Expand && isELF32_ABI) GPR_idx += (GPR_idx % 2);
if (GPR_idx != Num_GPR_Regs) { if (GPR_idx != Num_GPR_Regs) {
unsigned VReg = RegInfo.createVirtualRegister(&PPC::GPRCRegClass); unsigned VReg = RegInfo.createVirtualRegister(&PPC::GPRCRegClass);
RegInfo.addLiveIn(GPR[GPR_idx], VReg); RegInfo.addLiveIn(GPR[GPR_idx], VReg);
@ -1425,12 +1428,27 @@ SDOperand PPCTargetLowering::LowerFORMAL_ARGUMENTS(SDOperand Op,
// All int arguments reserve stack space in Macho ABI. // All int arguments reserve stack space in Macho ABI.
if (isMachoABI || needsLoad) ArgOffset += PtrByteSize; if (isMachoABI || needsLoad) ArgOffset += PtrByteSize;
break; break;
}
// FALLTHROUGH
case MVT::i64: // PPC64 case MVT::i64: // PPC64
if (GPR_idx != Num_GPR_Regs) { if (GPR_idx != Num_GPR_Regs) {
unsigned VReg = RegInfo.createVirtualRegister(&PPC::G8RCRegClass); unsigned VReg = RegInfo.createVirtualRegister(&PPC::G8RCRegClass);
RegInfo.addLiveIn(GPR[GPR_idx], VReg); RegInfo.addLiveIn(GPR[GPR_idx], VReg);
ArgVal = DAG.getCopyFromReg(Root, VReg, MVT::i64); ArgVal = DAG.getCopyFromReg(Root, VReg, MVT::i64);
if (ObjectVT == MVT::i32) {
// PPC64 passes i8, i16, and i32 values in i64 registers. Promote
// value to MVT::i64 and then truncate to the correct register size.
if (Flags & ISD::ParamFlags::SExt)
ArgVal = DAG.getNode(ISD::AssertSext, MVT::i64, ArgVal,
DAG.getValueType(ObjectVT));
else if (Flags & ISD::ParamFlags::ZExt)
ArgVal = DAG.getNode(ISD::AssertZext, MVT::i64, ArgVal,
DAG.getValueType(ObjectVT));
ArgVal = DAG.getNode(ISD::TRUNCATE, MVT::i32, ArgVal);
}
++GPR_idx; ++GPR_idx;
} else { } else {
needsLoad = true; needsLoad = true;
@ -1742,7 +1760,6 @@ SDOperand PPCTargetLowering::LowerCALL(SDOperand Op, SelectionDAG &DAG,
// On PPC64, promote integers to 64-bit values. // On PPC64, promote integers to 64-bit values.
if (isPPC64 && Arg.getValueType() == MVT::i32) { if (isPPC64 && Arg.getValueType() == MVT::i32) {
unsigned ExtOp = (Flags & 1) ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; unsigned ExtOp = (Flags & 1) ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
Arg = DAG.getNode(ExtOp, MVT::i64, Arg); Arg = DAG.getNode(ExtOp, MVT::i64, Arg);
} }