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Sparc specific methods default to abort rather than being pure virtual
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@5169 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -267,12 +267,15 @@ public:
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//-------------------------------------------------------------------------
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// Code generation support for creating individual machine instructions
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//
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// WARNING: These methods are Sparc specific
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//
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//-------------------------------------------------------------------------
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// Get certain common op codes for the current target. this and all the
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// Create* methods below should be moved to a machine code generation class
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//
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virtual MachineOpCode getNOPOpCode() const = 0;
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virtual MachineOpCode getNOPOpCode() const { abort(); }
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// Create an instruction sequence to put the constant `val' into
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// the virtual register `dest'. `val' may be a Constant or a
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@ -287,7 +290,9 @@ public:
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Value* val,
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Instruction* dest,
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std::vector<MachineInstr*>& mvec,
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MachineCodeForInstruction& mcfi) const=0;
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MachineCodeForInstruction& mcfi) const {
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abort();
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}
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// Create an instruction sequence to copy an integer value `val'
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// to a floating point value `dest' by copying to memory and back.
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@ -296,12 +301,14 @@ public:
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// Any temp. registers (TmpInstruction) created are recorded in mcfi.
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// Any stack space required is allocated via mcff.
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//
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virtual void CreateCodeToCopyIntToFloat(const TargetMachine& target,
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Function* F,
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Value* val,
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Instruction* dest,
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std::vector<MachineInstr*>& mvec,
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MachineCodeForInstruction& mcfi)const=0;
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virtual void CreateCodeToCopyIntToFloat(const TargetMachine& target,
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Function* F,
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Value* val,
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Instruction* dest,
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std::vector<MachineInstr*>& mvec,
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MachineCodeForInstruction& MI) const {
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abort();
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}
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// Similarly, create an instruction sequence to copy an FP value
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// `val' to an integer value `dest' by copying to memory and back.
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@ -309,12 +316,14 @@ public:
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// Any temp. registers (TmpInstruction) created are recorded in mcfi.
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// Any stack space required is allocated via mcff.
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//
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virtual void CreateCodeToCopyFloatToInt(const TargetMachine& target,
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Function* F,
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Value* val,
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Instruction* dest,
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std::vector<MachineInstr*>& mvec,
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MachineCodeForInstruction& mcfi)const=0;
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virtual void CreateCodeToCopyFloatToInt(const TargetMachine& target,
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Function* F,
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Value* val,
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Instruction* dest,
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std::vector<MachineInstr*>& mvec,
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MachineCodeForInstruction& MI) const {
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abort();
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}
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// Create instruction(s) to copy src to dest, for arbitrary types
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// The generated instructions are returned in `mvec'.
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@ -322,11 +331,13 @@ public:
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// Any stack space required is allocated via mcff.
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//
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virtual void CreateCopyInstructionsByType(const TargetMachine& target,
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Function* F,
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Value* src,
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Instruction* dest,
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std::vector<MachineInstr*>& mvec,
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MachineCodeForInstruction& mcfi)const=0;
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Function* F,
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Value* src,
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Instruction* dest,
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std::vector<MachineInstr*>& mvec,
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MachineCodeForInstruction& MI) const {
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abort();
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}
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// Create instruction sequence to produce a sign-extended register value
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// from an arbitrary sized value (sized in bits, not bytes).
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@ -340,7 +351,9 @@ public:
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Value* destVal,
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unsigned numLowBits,
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std::vector<MachineInstr*>& mvec,
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MachineCodeForInstruction& mcfi) const=0;
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MachineCodeForInstruction& MI) const {
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abort();
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}
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// Create instruction sequence to produce a zero-extended register value
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// from an arbitrary sized value (sized in bits, not bytes).
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@ -354,7 +367,9 @@ public:
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Value* destVal,
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unsigned srcSizeInBits,
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std::vector<MachineInstr*>& mvec,
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MachineCodeForInstruction& mcfi) const=0;
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MachineCodeForInstruction& mcfi) const {
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abort();
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}
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};
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#endif
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@ -267,12 +267,15 @@ public:
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//-------------------------------------------------------------------------
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// Code generation support for creating individual machine instructions
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//
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// WARNING: These methods are Sparc specific
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//
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//-------------------------------------------------------------------------
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// Get certain common op codes for the current target. this and all the
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// Create* methods below should be moved to a machine code generation class
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//
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virtual MachineOpCode getNOPOpCode() const = 0;
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virtual MachineOpCode getNOPOpCode() const { abort(); }
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// Create an instruction sequence to put the constant `val' into
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// the virtual register `dest'. `val' may be a Constant or a
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@ -287,7 +290,9 @@ public:
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Value* val,
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Instruction* dest,
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std::vector<MachineInstr*>& mvec,
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MachineCodeForInstruction& mcfi) const=0;
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MachineCodeForInstruction& mcfi) const {
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abort();
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}
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// Create an instruction sequence to copy an integer value `val'
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// to a floating point value `dest' by copying to memory and back.
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@ -296,12 +301,14 @@ public:
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// Any temp. registers (TmpInstruction) created are recorded in mcfi.
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// Any stack space required is allocated via mcff.
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//
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virtual void CreateCodeToCopyIntToFloat(const TargetMachine& target,
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Function* F,
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Value* val,
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Instruction* dest,
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std::vector<MachineInstr*>& mvec,
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MachineCodeForInstruction& mcfi)const=0;
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virtual void CreateCodeToCopyIntToFloat(const TargetMachine& target,
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Function* F,
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Value* val,
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Instruction* dest,
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std::vector<MachineInstr*>& mvec,
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MachineCodeForInstruction& MI) const {
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abort();
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}
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// Similarly, create an instruction sequence to copy an FP value
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// `val' to an integer value `dest' by copying to memory and back.
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@ -309,12 +316,14 @@ public:
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// Any temp. registers (TmpInstruction) created are recorded in mcfi.
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// Any stack space required is allocated via mcff.
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//
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virtual void CreateCodeToCopyFloatToInt(const TargetMachine& target,
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Function* F,
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Value* val,
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Instruction* dest,
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std::vector<MachineInstr*>& mvec,
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MachineCodeForInstruction& mcfi)const=0;
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virtual void CreateCodeToCopyFloatToInt(const TargetMachine& target,
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Function* F,
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Value* val,
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Instruction* dest,
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std::vector<MachineInstr*>& mvec,
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MachineCodeForInstruction& MI) const {
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abort();
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}
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// Create instruction(s) to copy src to dest, for arbitrary types
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// The generated instructions are returned in `mvec'.
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@ -322,11 +331,13 @@ public:
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// Any stack space required is allocated via mcff.
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//
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virtual void CreateCopyInstructionsByType(const TargetMachine& target,
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Function* F,
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Value* src,
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Instruction* dest,
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std::vector<MachineInstr*>& mvec,
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MachineCodeForInstruction& mcfi)const=0;
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Function* F,
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Value* src,
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Instruction* dest,
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std::vector<MachineInstr*>& mvec,
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MachineCodeForInstruction& MI) const {
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abort();
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}
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// Create instruction sequence to produce a sign-extended register value
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// from an arbitrary sized value (sized in bits, not bytes).
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@ -340,7 +351,9 @@ public:
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Value* destVal,
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unsigned numLowBits,
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std::vector<MachineInstr*>& mvec,
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MachineCodeForInstruction& mcfi) const=0;
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MachineCodeForInstruction& MI) const {
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abort();
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}
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// Create instruction sequence to produce a zero-extended register value
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// from an arbitrary sized value (sized in bits, not bytes).
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@ -354,7 +367,9 @@ public:
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Value* destVal,
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unsigned srcSizeInBits,
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std::vector<MachineInstr*>& mvec,
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MachineCodeForInstruction& mcfi) const=0;
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MachineCodeForInstruction& mcfi) const {
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abort();
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}
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};
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#endif
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