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s/std::vector/SmallVector/
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118648 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -128,7 +128,7 @@ class ARMOperand : public MCParsedAsmOperand {
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} Reg;
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struct {
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std::vector<unsigned> *Registers;
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SmallVector<unsigned, 32> *Registers;
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} RegList;
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struct {
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@ -203,7 +203,7 @@ public:
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return Reg.RegNum;
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}
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const std::vector<unsigned> &getRegList() const {
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const SmallVectorImpl<unsigned> &getRegList() const {
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assert(Kind == RegisterList && "Invalid access!");
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return *RegList.Registers;
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}
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@ -258,8 +258,8 @@ public:
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void addRegListOperands(MCInst &Inst, unsigned N) const {
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assert(N == 1 && "Invalid number of operands!");
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const std::vector<unsigned> &RegList = getRegList();
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for (std::vector<unsigned>::const_iterator
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const SmallVectorImpl<unsigned> &RegList = getRegList();
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for (SmallVectorImpl<unsigned>::const_iterator
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I = RegList.begin(), E = RegList.end(); I != E; ++I)
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Inst.addOperand(MCOperand::CreateReg(*I));
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}
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@ -325,11 +325,11 @@ public:
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}
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static ARMOperand *
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CreateRegList(std::vector<std::pair<unsigned, SMLoc> > &Regs,
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CreateRegList(const SmallVectorImpl<std::pair<unsigned, SMLoc> > &Regs,
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SMLoc S, SMLoc E) {
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ARMOperand *Op = new ARMOperand(RegisterList);
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Op->RegList.Registers = new std::vector<unsigned>();
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for (std::vector<std::pair<unsigned, SMLoc> >::iterator
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Op->RegList.Registers = new SmallVector<unsigned, 32>();
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for (SmallVectorImpl<std::pair<unsigned, SMLoc> >::const_iterator
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I = Regs.begin(), E = Regs.end(); I != E; ++I)
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Op->RegList.Registers->push_back(I->first);
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std::sort(Op->RegList.Registers->begin(), Op->RegList.Registers->end());
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@ -390,8 +390,8 @@ void ARMOperand::dump(raw_ostream &OS) const {
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case RegisterList: {
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OS << "<register_list ";
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const std::vector<unsigned> &RegList = getRegList();
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for (std::vector<unsigned>::const_iterator
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const SmallVectorImpl<unsigned> &RegList = getRegList();
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for (SmallVectorImpl<unsigned>::const_iterator
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I = RegList.begin(), E = RegList.end(); I != E; ) {
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OS << *I;
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if (++I < E) OS << ", ";
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@ -465,8 +465,7 @@ ARMOperand *ARMAsmParser::ParseRegisterList() {
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// Read the rest of the registers in the list.
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unsigned PrevRegNum = 0;
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std::vector<std::pair<unsigned, SMLoc> > Registers;
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Registers.reserve(32);
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SmallVector<std::pair<unsigned, SMLoc>, 32> Registers;
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do {
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bool IsRange = Parser.getTok().is(AsmToken::Minus);
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@ -510,7 +509,7 @@ ARMOperand *ARMAsmParser::ParseRegisterList() {
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Parser.Lex(); // Eat right curly brace token.
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// Verify the register list.
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std::vector<std::pair<unsigned, SMLoc> >::const_iterator
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SmallVectorImpl<std::pair<unsigned, SMLoc> >::const_iterator
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RI = Registers.begin(), RE = Registers.end();
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unsigned HighRegNum = RI->first;
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