6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-12-15 04:30:12 +00:00
Code Issues Projects Releases Wiki Activity

Retain alignment requirements for load->selects modified by DAGCombine

Browse Source 
DAGCombine may choose to rewrite graphs where two loads feed a select into
graphs where a select of two addresses feed a load. While it sanity checks the
loads to make sure they are broadly equivalent it currently just uses the
alignment restriction of the left node. In cases where the right node has
stronger alignment requiresment this may lead to bad codegen, such as generating
an aligned load where an unaligned load is required. This patch makes the
combine generate a load with an alignment that is the same as whichever is more
restrictive of the two alignments.

Tests included.

rdar://17762530

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214322 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Louis Gerbarg 2014-07-30 18:24:41 +00:00
parent 43b54db2a4
commit 5fb3c84898
2 changed files with 41 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
lib/CodeGen/SelectionDAG/DAGCombiner.cpp
View File

@ -11181,13 +11181,17 @@ bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDValue LHS,
}
SDValue Load;
// It is safe to replace the two loads if they have different alignments,
// but the new load must be the minimum (most restrictive) alignment of the
// inputs.
unsigned Alignment = std::min(LLD->getAlignment(),RLD->getAlignment());
if (LLD->getExtensionType() == ISD::NON_EXTLOAD) {
Load = DAG.getLoad(TheSelect->getValueType(0),
SDLoc(TheSelect),
// FIXME: Discards pointer and AA info.
LLD->getChain(), Addr, MachinePointerInfo(),
LLD->isVolatile(), LLD->isNonTemporal(),
LLD->isInvariant(), LLD->getAlignment());
LLD->isInvariant(), Alignment);
} else {
Load = DAG.getExtLoad(LLD->getExtensionType() == ISD::EXTLOAD ?
RLD->getExtensionType() : LLD->getExtensionType(),
@ -11196,7 +11200,7 @@ bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDValue LHS,
// FIXME: Discards pointer and AA info.
LLD->getChain(), Addr, MachinePointerInfo(),
LLD->getMemoryVT(), LLD->isVolatile(),
LLD->isNonTemporal(), LLD->getAlignment());
LLD->isNonTemporal(), Alignment);
}
// Users of the select now use the result of the load.

35
test/CodeGen/X86/x86-mixed-alignment-dagcombine.ll Normal file
View File

@ -0,0 +1,35 @@
; RUN: llc -mcpu=core2 -mattr=+64bit,+sse2 < %s | FileCheck %s
; DAGCombine may choose to rewrite 2 loads feeding a select as a select of
; addresses feeding a load. This test ensures that when it does that it creates
; a load with alignment equivalent to the most restrictive source load.
declare void @sink(<2 x double>)
define void @test1(i1 %cmp) align 2 {
%1 = alloca <2 x double>, align 16
%2 = alloca <2 x double>, align 8
%val = load <2 x double>* %1, align 16
%val2 = load <2 x double>* %2, align 8
%val3 = select i1 %cmp, <2 x double> %val, <2 x double> %val2
call void @sink(<2 x double> %val3)
ret void
; CHECK: test1
; CHECK: movups
; CHECK: ret
}
define void @test2(i1 %cmp) align 2 {
%1 = alloca <2 x double>, align 16
%2 = alloca <2 x double>, align 8
%val = load <2 x double>* %1, align 16
%val2 = load <2 x double>* %2, align 16
%val3 = select i1 %cmp, <2 x double> %val, <2 x double> %val2
call void @sink(<2 x double> %val3)
ret void
; CHECK: test2
; CHECK: movaps
; CHECK: ret
}