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[X86] Remove unnecessary alignment checks from the load folding tables.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228671 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Craig Topper 2015-02-10 05:10:50 +00:00
parent afd23204f0
commit 5fc4b96e62
1 changed files with 44 additions and 44 deletions
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88
lib/Target/X86/X86InstrInfo.cpp
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@ -1069,14 +1069,14 @@ X86InstrInfo::X86InstrInfo(X86Subtarget &STI)
{ X86::VDIVSSrr_Int, X86::VDIVSSrm_Int, 0 },
{ X86::VDPPDrri, X86::VDPPDrmi, 0 },
{ X86::VDPPSrri, X86::VDPPSrmi, 0 },
{ X86::VFsANDNPDrr, X86::VFsANDNPDrm, TB_ALIGN_16 },
{ X86::VFsANDNPSrr, X86::VFsANDNPSrm, TB_ALIGN_16 },
{ X86::VFsANDPDrr, X86::VFsANDPDrm, TB_ALIGN_16 },
{ X86::VFsANDPSrr, X86::VFsANDPSrm, TB_ALIGN_16 },
{ X86::VFsORPDrr, X86::VFsORPDrm, TB_ALIGN_16 },
{ X86::VFsORPSrr, X86::VFsORPSrm, TB_ALIGN_16 },
{ X86::VFsXORPDrr, X86::VFsXORPDrm, TB_ALIGN_16 },
{ X86::VFsXORPSrr, X86::VFsXORPSrm, TB_ALIGN_16 },
{ X86::VFsANDNPDrr, X86::VFsANDNPDrm, 0 },
{ X86::VFsANDNPSrr, X86::VFsANDNPSrm, 0 },
{ X86::VFsANDPDrr, X86::VFsANDPDrm, 0 },
{ X86::VFsANDPSrr, X86::VFsANDPSrm, 0 },
{ X86::VFsORPDrr, X86::VFsORPDrm, 0 },
{ X86::VFsORPSrr, X86::VFsORPSrm, 0 },
{ X86::VFsXORPDrr, X86::VFsXORPDrm, 0 },
{ X86::VFsXORPSrr, X86::VFsXORPSrm, 0 },
{ X86::VHADDPDrr, X86::VHADDPDrm, 0 },
{ X86::VHADDPSrr, X86::VHADDPSrm, 0 },
{ X86::VHSUBPDrr, X86::VHSUBPDrm, 0 },
@ -1358,38 +1358,38 @@ X86InstrInfo::X86InstrInfo(X86Subtarget &STI)
// FIXME: add AVX 256-bit foldable instructions
// FMA4 foldable patterns
{ X86::VFMADDSS4rr, X86::VFMADDSS4mr, 0 },
{ X86::VFMADDSD4rr, X86::VFMADDSD4mr, 0 },
{ X86::VFMADDPS4rr, X86::VFMADDPS4mr, TB_ALIGN_16 },
{ X86::VFMADDPD4rr, X86::VFMADDPD4mr, TB_ALIGN_16 },
{ X86::VFMADDPS4rrY, X86::VFMADDPS4mrY, TB_ALIGN_32 },
{ X86::VFMADDPD4rrY, X86::VFMADDPD4mrY, TB_ALIGN_32 },
{ X86::VFNMADDSS4rr, X86::VFNMADDSS4mr, 0 },
{ X86::VFNMADDSD4rr, X86::VFNMADDSD4mr, 0 },
{ X86::VFNMADDPS4rr, X86::VFNMADDPS4mr, TB_ALIGN_16 },
{ X86::VFNMADDPD4rr, X86::VFNMADDPD4mr, TB_ALIGN_16 },
{ X86::VFNMADDPS4rrY, X86::VFNMADDPS4mrY, TB_ALIGN_32 },
{ X86::VFNMADDPD4rrY, X86::VFNMADDPD4mrY, TB_ALIGN_32 },
{ X86::VFMSUBSS4rr, X86::VFMSUBSS4mr, 0 },
{ X86::VFMSUBSD4rr, X86::VFMSUBSD4mr, 0 },
{ X86::VFMSUBPS4rr, X86::VFMSUBPS4mr, TB_ALIGN_16 },
{ X86::VFMSUBPD4rr, X86::VFMSUBPD4mr, TB_ALIGN_16 },
{ X86::VFMSUBPS4rrY, X86::VFMSUBPS4mrY, TB_ALIGN_32 },
{ X86::VFMSUBPD4rrY, X86::VFMSUBPD4mrY, TB_ALIGN_32 },
{ X86::VFNMSUBSS4rr, X86::VFNMSUBSS4mr, 0 },
{ X86::VFNMSUBSD4rr, X86::VFNMSUBSD4mr, 0 },
{ X86::VFNMSUBPS4rr, X86::VFNMSUBPS4mr, TB_ALIGN_16 },
{ X86::VFNMSUBPD4rr, X86::VFNMSUBPD4mr, TB_ALIGN_16 },
{ X86::VFNMSUBPS4rrY, X86::VFNMSUBPS4mrY, TB_ALIGN_32 },
{ X86::VFNMSUBPD4rrY, X86::VFNMSUBPD4mrY, TB_ALIGN_32 },
{ X86::VFMADDSUBPS4rr, X86::VFMADDSUBPS4mr, TB_ALIGN_16 },
{ X86::VFMADDSUBPD4rr, X86::VFMADDSUBPD4mr, TB_ALIGN_16 },
{ X86::VFMADDSUBPS4rrY, X86::VFMADDSUBPS4mrY, TB_ALIGN_32 },
{ X86::VFMADDSUBPD4rrY, X86::VFMADDSUBPD4mrY, TB_ALIGN_32 },
{ X86::VFMSUBADDPS4rr, X86::VFMSUBADDPS4mr, TB_ALIGN_16 },
{ X86::VFMSUBADDPD4rr, X86::VFMSUBADDPD4mr, TB_ALIGN_16 },
{ X86::VFMSUBADDPS4rrY, X86::VFMSUBADDPS4mrY, TB_ALIGN_32 },
{ X86::VFMSUBADDPD4rrY, X86::VFMSUBADDPD4mrY, TB_ALIGN_32 },
{ X86::VFMADDSS4rr, X86::VFMADDSS4mr, 0 },
{ X86::VFMADDSD4rr, X86::VFMADDSD4mr, 0 },
{ X86::VFMADDPS4rr, X86::VFMADDPS4mr, 0 },
{ X86::VFMADDPD4rr, X86::VFMADDPD4mr, 0 },
{ X86::VFMADDPS4rrY, X86::VFMADDPS4mrY, 0 },
{ X86::VFMADDPD4rrY, X86::VFMADDPD4mrY, 0 },
{ X86::VFNMADDSS4rr, X86::VFNMADDSS4mr, 0 },
{ X86::VFNMADDSD4rr, X86::VFNMADDSD4mr, 0 },
{ X86::VFNMADDPS4rr, X86::VFNMADDPS4mr, 0 },
{ X86::VFNMADDPD4rr, X86::VFNMADDPD4mr, 0 },
{ X86::VFNMADDPS4rrY, X86::VFNMADDPS4mrY, 0 },
{ X86::VFNMADDPD4rrY, X86::VFNMADDPD4mrY, 0 },
{ X86::VFMSUBSS4rr, X86::VFMSUBSS4mr, 0 },
{ X86::VFMSUBSD4rr, X86::VFMSUBSD4mr, 0 },
{ X86::VFMSUBPS4rr, X86::VFMSUBPS4mr, 0 },
{ X86::VFMSUBPD4rr, X86::VFMSUBPD4mr, 0 },
{ X86::VFMSUBPS4rrY, X86::VFMSUBPS4mrY, 0 },
{ X86::VFMSUBPD4rrY, X86::VFMSUBPD4mrY, 0 },
{ X86::VFNMSUBSS4rr, X86::VFNMSUBSS4mr, 0 },
{ X86::VFNMSUBSD4rr, X86::VFNMSUBSD4mr, 0 },
{ X86::VFNMSUBPS4rr, X86::VFNMSUBPS4mr, 0 },
{ X86::VFNMSUBPD4rr, X86::VFNMSUBPD4mr, 0 },
{ X86::VFNMSUBPS4rrY, X86::VFNMSUBPS4mrY, 0 },
{ X86::VFNMSUBPD4rrY, X86::VFNMSUBPD4mrY, 0 },
{ X86::VFMADDSUBPS4rr, X86::VFMADDSUBPS4mr, 0 },
{ X86::VFMADDSUBPD4rr, X86::VFMADDSUBPD4mr, 0 },
{ X86::VFMADDSUBPS4rrY, X86::VFMADDSUBPS4mrY, 0 },
{ X86::VFMADDSUBPD4rrY, X86::VFMADDSUBPD4mrY, 0 },
{ X86::VFMSUBADDPS4rr, X86::VFMSUBADDPS4mr, 0 },
{ X86::VFMSUBADDPD4rr, X86::VFMSUBADDPD4mr, 0 },
{ X86::VFMSUBADDPS4rrY, X86::VFMSUBADDPS4mrY, 0 },
{ X86::VFMSUBADDPD4rrY, X86::VFMSUBADDPD4mrY, 0 },
// BMI/BMI2 foldable instructions
{ X86::ANDN32rr, X86::ANDN32rm, 0 },
@ -1458,10 +1458,10 @@ X86InstrInfo::X86InstrInfo(X86Subtarget &STI)
{ X86::AESDECrr, X86::AESDECrm, TB_ALIGN_16 },
{ X86::AESENCLASTrr, X86::AESENCLASTrm, TB_ALIGN_16 },
{ X86::AESENCrr, X86::AESENCrm, TB_ALIGN_16 },
{ X86::VAESDECLASTrr, X86::VAESDECLASTrm, TB_ALIGN_16 },
{ X86::VAESDECrr, X86::VAESDECrm, TB_ALIGN_16 },
{ X86::VAESENCLASTrr, X86::VAESENCLASTrm, TB_ALIGN_16 },
{ X86::VAESENCrr, X86::VAESENCrm, TB_ALIGN_16 },
{ X86::VAESDECLASTrr, X86::VAESDECLASTrm, 0 },
{ X86::VAESDECrr, X86::VAESDECrm, 0 },
{ X86::VAESENCLASTrr, X86::VAESENCLASTrm, 0 },
{ X86::VAESENCrr, X86::VAESENCrm, 0 },
// SHA foldable instructions
{ X86::SHA1MSG1rr, X86::SHA1MSG1rm, TB_ALIGN_16 },