From 5ffe38ef6ae3427b39b2d866ab8d1a73f9f69e56 Mon Sep 17 00:00:00 2001 From: Chris Lattner Date: Mon, 15 Nov 2010 04:16:32 +0000 Subject: [PATCH] Implement a basic MCCodeEmitter for PPC. This doesn't handle fixups yet, and doesn't handle actually encoding operand values, but this is enough for llc -show-mc-encoding to show the base instruction encoding information, e.g.: mflr r0 ; encoding: [0x7c,0x08,0x02,0xa6] stw r0, 8(r1) ; encoding: [0x90,0x00,0x00,0x00] stwu r1, -64(r1) ; encoding: [0x94,0x00,0x00,0x00] Ltmp0: lhz r4, 4(r3) ; encoding: [0xa0,0x00,0x00,0x00] cmplwi cr0, r4, 8 ; encoding: [0x28,0x00,0x00,0x00] beq cr0, LBB0_2 ; encoding: [0x40,0x00,0x00,0x00] git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119116 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/PowerPC/CMakeLists.txt | 2 + lib/Target/PowerPC/Makefile | 3 +- lib/Target/PowerPC/PPC.h | 7 +- lib/Target/PowerPC/PPCMCCodeEmitter.cpp | 99 +++++++++++++++++++++++++ lib/Target/PowerPC/PPCTargetMachine.cpp | 4 + 5 files changed, 113 insertions(+), 2 deletions(-) create mode 100644 lib/Target/PowerPC/PPCMCCodeEmitter.cpp diff --git a/lib/Target/PowerPC/CMakeLists.txt b/lib/Target/PowerPC/CMakeLists.txt index 0ca192123f6..923c079e79b 100644 --- a/lib/Target/PowerPC/CMakeLists.txt +++ b/lib/Target/PowerPC/CMakeLists.txt @@ -4,6 +4,7 @@ tablegen(PPCGenInstrNames.inc -gen-instr-enums) tablegen(PPCGenRegisterNames.inc -gen-register-enums) tablegen(PPCGenAsmWriter.inc -gen-asm-writer) tablegen(PPCGenCodeEmitter.inc -gen-emitter) +tablegen(PPCGenMCCodeEmitter.inc -gen-emitter -mc-emitter) tablegen(PPCGenRegisterInfo.h.inc -gen-register-desc-header) tablegen(PPCGenRegisterInfo.inc -gen-register-desc) tablegen(PPCGenInstrInfo.inc -gen-instr-desc) @@ -22,6 +23,7 @@ add_llvm_target(PowerPCCodeGen PPCFrameInfo.cpp PPCJITInfo.cpp PPCMCAsmInfo.cpp + PPCMCCodeEmitter.cpp PPCMCInstLower.cpp PPCPredicates.cpp PPCRegisterInfo.cpp diff --git a/lib/Target/PowerPC/Makefile b/lib/Target/PowerPC/Makefile index 484aa9849e9..030defe212c 100644 --- a/lib/Target/PowerPC/Makefile +++ b/lib/Target/PowerPC/Makefile @@ -16,7 +16,8 @@ BUILT_SOURCES = PPCGenInstrNames.inc PPCGenRegisterNames.inc \ PPCGenAsmWriter.inc PPCGenCodeEmitter.inc \ PPCGenRegisterInfo.h.inc PPCGenRegisterInfo.inc \ PPCGenInstrInfo.inc PPCGenDAGISel.inc \ - PPCGenSubtarget.inc PPCGenCallingConv.inc + PPCGenSubtarget.inc PPCGenCallingConv.inc \ + PPCGenMCCodeEmitter.inc DIRS = InstPrinter TargetInfo diff --git a/lib/Target/PowerPC/PPC.h b/lib/Target/PowerPC/PPC.h index 460d8e1744e..dbe98a68dbe 100644 --- a/lib/Target/PowerPC/PPC.h +++ b/lib/Target/PowerPC/PPC.h @@ -25,13 +25,18 @@ namespace llvm { class JITCodeEmitter; class Target; class MachineInstr; - class MCInst; class AsmPrinter; + class MCInst; + class MCCodeEmitter; + class MCContext; + class TargetMachine; FunctionPass *createPPCBranchSelectionPass(); FunctionPass *createPPCISelDag(PPCTargetMachine &TM); FunctionPass *createPPCJITCodeEmitterPass(PPCTargetMachine &TM, JITCodeEmitter &MCE); + MCCodeEmitter *createPPCMCCodeEmitter(const Target &, TargetMachine &TM, + MCContext &Ctx); void LowerPPCMachineInstrToMCInst(const MachineInstr *MI, MCInst &OutMI, AsmPrinter &AP); diff --git a/lib/Target/PowerPC/PPCMCCodeEmitter.cpp b/lib/Target/PowerPC/PPCMCCodeEmitter.cpp new file mode 100644 index 00000000000..ecff0e8b2b3 --- /dev/null +++ b/lib/Target/PowerPC/PPCMCCodeEmitter.cpp @@ -0,0 +1,99 @@ +//===-- PPCMCCodeEmitter.cpp - Convert PPC code to machine code -----------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file implements the PPCMCCodeEmitter class. +// +//===----------------------------------------------------------------------===// + +#define DEBUG_TYPE "mccodeemitter" +#include "PPC.h" +#include "llvm/MC/MCCodeEmitter.h" +#include "llvm/MC/MCInst.h" +#include "llvm/ADT/Statistic.h" +#include "llvm/Support/raw_ostream.h" +#include "llvm/Support/ErrorHandling.h" +using namespace llvm; + +STATISTIC(MCNumEmitted, "Number of MC instructions emitted"); + +namespace { +class PPCMCCodeEmitter : public MCCodeEmitter { + PPCMCCodeEmitter(const PPCMCCodeEmitter &); // DO NOT IMPLEMENT + void operator=(const PPCMCCodeEmitter &); // DO NOT IMPLEMENT + const TargetMachine &TM; + MCContext &Ctx; + +public: + PPCMCCodeEmitter(TargetMachine &tm, MCContext &ctx) + : TM(tm), Ctx(ctx) { + } + + ~PPCMCCodeEmitter() {} + + unsigned getNumFixupKinds() const { return 0 /*PPC::NumTargetFixupKinds*/; } + + const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const { + const static MCFixupKindInfo Infos[] = { +#if 0 + // name offset bits flags + { "fixup_arm_pcrel_12", 2, 12, MCFixupKindInfo::FKF_IsPCRel }, + { "fixup_arm_vfp_pcrel_12", 3, 8, MCFixupKindInfo::FKF_IsPCRel }, + { "fixup_arm_branch", 1, 24, MCFixupKindInfo::FKF_IsPCRel }, +#endif + }; + + if (Kind < FirstTargetFixupKind) + return MCCodeEmitter::getFixupKindInfo(Kind); + + assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() && + "Invalid kind!"); + return Infos[Kind - FirstTargetFixupKind]; + } + + /// getMachineOpValue - Return binary encoding of operand. If the machine + /// operand requires relocation, record the relocation and return zero. + unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO, + SmallVectorImpl &Fixups) const; + + + // getBinaryCodeForInstr - TableGen'erated function for getting the + // binary encoding for an instruction. + unsigned getBinaryCodeForInstr(const MCInst &MI, + SmallVectorImpl &Fixups) const; + void EncodeInstruction(const MCInst &MI, raw_ostream &OS, + SmallVectorImpl &Fixups) const { + unsigned Bits = getBinaryCodeForInstr(MI, Fixups); + + // Output the constant in big endian byte order. + for (unsigned i = 0; i != 4; ++i) { + OS << (char)(Bits >> 24); + Bits <<= 8; + } + + ++MCNumEmitted; // Keep track of the # of mi's emitted. + } + +}; + +} // end anonymous namespace + +MCCodeEmitter *llvm::createPPCMCCodeEmitter(const Target &, TargetMachine &TM, + MCContext &Ctx) { + return new PPCMCCodeEmitter(TM, Ctx); +} + +unsigned PPCMCCodeEmitter:: +getMachineOpValue(const MCInst &MI, const MCOperand &MO, + SmallVectorImpl &Fixups) const { + // FIXME. + return 0; +} + + +#include "PPCGenMCCodeEmitter.inc" diff --git a/lib/Target/PowerPC/PPCTargetMachine.cpp b/lib/Target/PowerPC/PPCTargetMachine.cpp index 307f36087d2..7946837e06c 100644 --- a/lib/Target/PowerPC/PPCTargetMachine.cpp +++ b/lib/Target/PowerPC/PPCTargetMachine.cpp @@ -36,6 +36,10 @@ extern "C" void LLVMInitializePowerPCTarget() { RegisterAsmInfoFn C(ThePPC32Target, createMCAsmInfo); RegisterAsmInfoFn D(ThePPC64Target, createMCAsmInfo); + + // Register the MC Code Emitter + TargetRegistry::RegisterCodeEmitter(ThePPC32Target, createPPCMCCodeEmitter); + TargetRegistry::RegisterCodeEmitter(ThePPC64Target, createPPCMCCodeEmitter); }