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RISC architectures get their memory operand folding for free.

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The only folding these load/store architectures can do is converting COPY into a
load or store, and the target independent part of foldMemoryOperand already
knows how to do that.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108099 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jakob Stoklund Olesen
2010-07-11 19:19:13 +00:00
parent a66450d227
commit 600f171486
16 changed files with 0 additions and 812 deletions
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115
lib/Target/PowerPC/PPCInstrInfo.cpp
View File

@@ -649,121 +649,6 @@ PPCInstrInfo::emitFrameIndexDebugValue(MachineFunction &MF,
return &*MIB;
}
/// foldMemoryOperand - PowerPC (like most RISC's) can only fold spills into
/// copy instructions, turning them into load/store instructions.
MachineInstr *PPCInstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
MachineInstr *MI,
const SmallVectorImpl<unsigned> &Ops,
int FrameIndex) const {
if (Ops.size() != 1) return NULL;
// Make sure this is a reg-reg copy. Note that we can't handle MCRF, because
// it takes more than one instruction to store it.
unsigned Opc = MI->getOpcode();
unsigned OpNum = Ops[0];
MachineInstr *NewMI = NULL;
if ((Opc == PPC::OR &&
MI->getOperand(1).getReg() == MI->getOperand(2).getReg())) {
if (OpNum == 0) { // move -> store
unsigned InReg = MI->getOperand(1).getReg();
bool isKill = MI->getOperand(1).isKill();
bool isUndef = MI->getOperand(1).isUndef();
NewMI = addFrameReference(BuildMI(MF, MI->getDebugLoc(), get(PPC::STW))
.addReg(InReg,
getKillRegState(isKill) |
getUndefRegState(isUndef)),
FrameIndex);
} else { // move -> load
unsigned OutReg = MI->getOperand(0).getReg();
bool isDead = MI->getOperand(0).isDead();
bool isUndef = MI->getOperand(0).isUndef();
NewMI = addFrameReference(BuildMI(MF, MI->getDebugLoc(), get(PPC::LWZ))
.addReg(OutReg,
RegState::Define |
getDeadRegState(isDead) |
getUndefRegState(isUndef)),
FrameIndex);
}
} else if ((Opc == PPC::OR8 &&
MI->getOperand(1).getReg() == MI->getOperand(2).getReg())) {
if (OpNum == 0) { // move -> store
unsigned InReg = MI->getOperand(1).getReg();
bool isKill = MI->getOperand(1).isKill();
bool isUndef = MI->getOperand(1).isUndef();
NewMI = addFrameReference(BuildMI(MF, MI->getDebugLoc(), get(PPC::STD))
.addReg(InReg,
getKillRegState(isKill) |
getUndefRegState(isUndef)),
FrameIndex);
} else { // move -> load
unsigned OutReg = MI->getOperand(0).getReg();
bool isDead = MI->getOperand(0).isDead();
bool isUndef = MI->getOperand(0).isUndef();
NewMI = addFrameReference(BuildMI(MF, MI->getDebugLoc(), get(PPC::LD))
.addReg(OutReg,
RegState::Define |
getDeadRegState(isDead) |
getUndefRegState(isUndef)),
FrameIndex);
}
} else if (Opc == PPC::FMR || Opc == PPC::FMRSD) {
// The register may be F4RC or F8RC, and that determines the memory op.
unsigned OrigReg = MI->getOperand(OpNum).getReg();
// We cannot tell the register class from a physreg alone.
if (TargetRegisterInfo::isPhysicalRegister(OrigReg))
return NULL;
const TargetRegisterClass *RC = MF.getRegInfo().getRegClass(OrigReg);
const bool is64 = RC == PPC::F8RCRegisterClass;
if (OpNum == 0) { // move -> store
unsigned InReg = MI->getOperand(1).getReg();
bool isKill = MI->getOperand(1).isKill();
bool isUndef = MI->getOperand(1).isUndef();
NewMI = addFrameReference(BuildMI(MF, MI->getDebugLoc(),
get(is64 ? PPC::STFD : PPC::STFS))
.addReg(InReg,
getKillRegState(isKill) |
getUndefRegState(isUndef)),
FrameIndex);
} else { // move -> load
unsigned OutReg = MI->getOperand(0).getReg();
bool isDead = MI->getOperand(0).isDead();
bool isUndef = MI->getOperand(0).isUndef();
NewMI = addFrameReference(BuildMI(MF, MI->getDebugLoc(),
get(is64 ? PPC::LFD : PPC::LFS))
.addReg(OutReg,
RegState::Define |
getDeadRegState(isDead) |
getUndefRegState(isUndef)),
FrameIndex);
}
}
return NewMI;
}
bool PPCInstrInfo::canFoldMemoryOperand(const MachineInstr *MI,
const SmallVectorImpl<unsigned> &Ops) const {
if (Ops.size() != 1) return false;
// Make sure this is a reg-reg copy. Note that we can't handle MCRF, because
// it takes more than one instruction to store it.
unsigned Opc = MI->getOpcode();
if ((Opc == PPC::OR &&
MI->getOperand(1).getReg() == MI->getOperand(2).getReg()))
return true;
else if ((Opc == PPC::OR8 &&
MI->getOperand(1).getReg() == MI->getOperand(2).getReg()))
return true;
else if (Opc == PPC::FMR || Opc == PPC::FMRSD)
return true;
return false;
}
bool PPCInstrInfo::
ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
assert(Cond.size() == 2 && "Invalid PPC branch opcode!");