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Fix the ARM IIC_iCMPsi itinerary and add an important assert.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122794 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -123,7 +123,8 @@ def CortexA9Itineraries : ProcessorItineraries<
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InstrItinData<IIC_iCMPr , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
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InstrStage<1, [A9_ALU0, A9_ALU1]>],
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[1, 1], [A9_LdBypass, A9_LdBypass]>,
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InstrItinData<IIC_iCMPsi , [InstrStage<2, [A9_ALU0, A9_ALU1]>],
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InstrItinData<IIC_iCMPsi , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
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InstrStage<2, [A9_ALU0, A9_ALU1]>],
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[1, 1], [A9_LdBypass, NoBypass]>,
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InstrItinData<IIC_iCMPsr , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
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InstrStage<3, [A9_ALU0, A9_ALU1]>],
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@ -240,6 +240,7 @@ void ARMSubtarget::computeIssueWidth() {
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// clear the lowest bit
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allStage1Units ^= allStage1Units & ~(allStage1Units - 1);
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}
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assert(InstrItins.IssueWidth <= 2 && "itinerary bug, too many stage 1 units");
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}
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bool ARMSubtarget::enablePostRAScheduler(
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