mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-17 21:29:20 +00:00
Enable two-address remat by default.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52701 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
parent
e4f6ee590b
commit
601ca4b434
@ -53,10 +53,6 @@ STATISTIC(NumConvertedTo3Addr, "Number of instructions promoted to 3-address");
|
|||||||
STATISTIC(Num3AddrSunk, "Number of 3-address instructions sunk");
|
STATISTIC(Num3AddrSunk, "Number of 3-address instructions sunk");
|
||||||
STATISTIC(NumReMats, "Number of instructions re-materialized");
|
STATISTIC(NumReMats, "Number of instructions re-materialized");
|
||||||
|
|
||||||
static cl::opt<bool>
|
|
||||||
EnableReMat("two-addr-remat", cl::init(false), cl::Hidden,
|
|
||||||
cl::desc("Two-addr conversion should remat when possible."));
|
|
||||||
|
|
||||||
namespace {
|
namespace {
|
||||||
class VISIBILITY_HIDDEN TwoAddressInstructionPass
|
class VISIBILITY_HIDDEN TwoAddressInstructionPass
|
||||||
: public MachineFunctionPass {
|
: public MachineFunctionPass {
|
||||||
@ -71,8 +67,8 @@ namespace {
|
|||||||
|
|
||||||
bool isSafeToReMat(unsigned DstReg, MachineInstr *MI);
|
bool isSafeToReMat(unsigned DstReg, MachineInstr *MI);
|
||||||
bool isProfitableToReMat(unsigned Reg, const TargetRegisterClass *RC,
|
bool isProfitableToReMat(unsigned Reg, const TargetRegisterClass *RC,
|
||||||
MachineInstr *MI, unsigned Loc,
|
MachineInstr *MI, MachineInstr *DefMI,
|
||||||
MachineInstr *DefMI, MachineBasicBlock *MBB,
|
MachineBasicBlock *MBB, unsigned Loc,
|
||||||
DenseMap<MachineInstr*, unsigned> &DistanceMap);
|
DenseMap<MachineInstr*, unsigned> &DistanceMap);
|
||||||
public:
|
public:
|
||||||
static char ID; // Pass identification, replacement for typeid
|
static char ID; // Pass identification, replacement for typeid
|
||||||
@ -248,12 +244,9 @@ static bool isTwoAddrUse(MachineInstr *UseMI, unsigned Reg) {
|
|||||||
bool
|
bool
|
||||||
TwoAddressInstructionPass::isProfitableToReMat(unsigned Reg,
|
TwoAddressInstructionPass::isProfitableToReMat(unsigned Reg,
|
||||||
const TargetRegisterClass *RC,
|
const TargetRegisterClass *RC,
|
||||||
MachineInstr *MI, unsigned Loc,
|
MachineInstr *MI, MachineInstr *DefMI,
|
||||||
MachineInstr *DefMI, MachineBasicBlock *MBB,
|
MachineBasicBlock *MBB, unsigned Loc,
|
||||||
DenseMap<MachineInstr*, unsigned> &DistanceMap) {
|
DenseMap<MachineInstr*, unsigned> &DistanceMap){
|
||||||
if (DefMI->getParent() != MBB)
|
|
||||||
return true;
|
|
||||||
// If earlier uses in MBB are not two-address uses, then don't remat.
|
|
||||||
bool OtherUse = false;
|
bool OtherUse = false;
|
||||||
for (MachineRegisterInfo::use_iterator UI = MRI->use_begin(Reg),
|
for (MachineRegisterInfo::use_iterator UI = MRI->use_begin(Reg),
|
||||||
UE = MRI->use_end(); UI != UE; ++UI) {
|
UE = MRI->use_end(); UI != UE; ++UI) {
|
||||||
@ -261,18 +254,26 @@ TwoAddressInstructionPass::isProfitableToReMat(unsigned Reg,
|
|||||||
if (!UseMO.isUse())
|
if (!UseMO.isUse())
|
||||||
continue;
|
continue;
|
||||||
MachineInstr *UseMI = UseMO.getParent();
|
MachineInstr *UseMI = UseMO.getParent();
|
||||||
if (UseMI->getParent() != MBB)
|
MachineBasicBlock *UseMBB = UseMI->getParent();
|
||||||
continue;
|
if (UseMBB == MBB) {
|
||||||
DenseMap<MachineInstr*, unsigned>::iterator DI = DistanceMap.find(UseMI);
|
DenseMap<MachineInstr*, unsigned>::iterator DI = DistanceMap.find(UseMI);
|
||||||
if (DI != DistanceMap.end() && DI->second == Loc)
|
if (DI != DistanceMap.end() && DI->second == Loc)
|
||||||
continue; // Current use.
|
continue; // Current use.
|
||||||
OtherUse = true;
|
OtherUse = true;
|
||||||
// There is at least one other use in the MBB that will clobber the
|
// There is at least one other use in the MBB that will clobber the
|
||||||
// register.
|
// register.
|
||||||
if (isTwoAddrUse(UseMI, Reg))
|
if (isTwoAddrUse(UseMI, Reg))
|
||||||
return true;
|
return true;
|
||||||
|
}
|
||||||
}
|
}
|
||||||
return !OtherUse;
|
|
||||||
|
// If other uses in MBB are not two-address uses, then don't remat.
|
||||||
|
if (OtherUse)
|
||||||
|
return false;
|
||||||
|
|
||||||
|
// No other uses in the same block, remat if it's defined in the same
|
||||||
|
// block so it does not unnecessarily extend the live range.
|
||||||
|
return MBB == DefMI->getParent();
|
||||||
}
|
}
|
||||||
|
|
||||||
/// runOnMachineFunction - Reduce two-address instructions to two operands.
|
/// runOnMachineFunction - Reduce two-address instructions to two operands.
|
||||||
@ -428,9 +429,9 @@ bool TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &MF) {
|
|||||||
MachineInstr *DefMI = MRI->getVRegDef(regB);
|
MachineInstr *DefMI = MRI->getVRegDef(regB);
|
||||||
// If it's safe and profitable, remat the definition instead of
|
// If it's safe and profitable, remat the definition instead of
|
||||||
// copying it.
|
// copying it.
|
||||||
if (EnableReMat && DefMI &&
|
if (DefMI &&
|
||||||
isSafeToReMat(regB, DefMI) &&
|
isSafeToReMat(regB, DefMI) &&
|
||||||
isProfitableToReMat(regB, rc, mi, Dist, DefMI, mbbi,DistanceMap)){
|
isProfitableToReMat(regB, rc, mi, DefMI, mbbi, Dist,DistanceMap)){
|
||||||
DEBUG(cerr << "2addr: REMATTING : " << *DefMI << "\n");
|
DEBUG(cerr << "2addr: REMATTING : " << *DefMI << "\n");
|
||||||
TII->reMaterialize(*mbbi, mi, regA, DefMI);
|
TII->reMaterialize(*mbbi, mi, regA, DefMI);
|
||||||
ReMatRegs.set(regB);
|
ReMatRegs.set(regB);
|
||||||
@ -473,17 +474,14 @@ bool TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &MF) {
|
|||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
if (EnableReMat) {
|
// Some remat'ed instructions are dead.
|
||||||
// Some remat'ed instructions are dead.
|
int VReg = ReMatRegs.find_first();
|
||||||
int VReg = ReMatRegs.find_first();
|
while (VReg != -1) {
|
||||||
while (VReg != -1) {
|
if (MRI->use_empty(VReg)) {
|
||||||
if (MRI->use_empty(VReg)) {
|
MachineInstr *DefMI = MRI->getVRegDef(VReg);
|
||||||
MachineInstr *DefMI = MRI->getVRegDef(VReg);
|
DefMI->eraseFromParent();
|
||||||
DefMI->eraseFromParent();
|
|
||||||
}
|
|
||||||
VReg = ReMatRegs.find_next(VReg);
|
|
||||||
}
|
}
|
||||||
|
VReg = ReMatRegs.find_next(VReg);
|
||||||
}
|
}
|
||||||
|
|
||||||
return MadeChange;
|
return MadeChange;
|
||||||
|
@ -199,7 +199,7 @@ let neverHasSideEffects = 1 in
|
|||||||
def MOV64rr : RI<0x89, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
|
def MOV64rr : RI<0x89, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
|
||||||
"mov{q}\t{$src, $dst|$dst, $src}", []>;
|
"mov{q}\t{$src, $dst|$dst, $src}", []>;
|
||||||
|
|
||||||
let isReMaterializable = 1 in {
|
let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
|
||||||
def MOV64ri : RIi64<0xB8, AddRegFrm, (outs GR64:$dst), (ins i64imm:$src),
|
def MOV64ri : RIi64<0xB8, AddRegFrm, (outs GR64:$dst), (ins i64imm:$src),
|
||||||
"movabs{q}\t{$src, $dst|$dst, $src}",
|
"movabs{q}\t{$src, $dst|$dst, $src}",
|
||||||
[(set GR64:$dst, imm:$src)]>;
|
[(set GR64:$dst, imm:$src)]>;
|
||||||
|
@ -3,7 +3,7 @@
|
|||||||
|
|
||||||
declare fastcc void @rdft(i32, i32, double*, i32*, double*)
|
declare fastcc void @rdft(i32, i32, double*, i32*, double*)
|
||||||
|
|
||||||
define fastcc void @mp_sqrt(i32 %n, i32 %radix, i32* %in, i32* %out, i32* %tmp1, i32* %tmp2, i32 %nfft, double* %tmp1fft, double* %tmp2fft, i32* %ip, double* %w) {
|
define fastcc void @mp_sqrt(i32 %n, i32 %radix, i32* %in, i32* %out, i32* %tmp1, i32* %tmp2, i32 %nfft, double* %tmp1fft, double* %tmp2fft, i32* %ip, double* %w) nounwind {
|
||||||
entry:
|
entry:
|
||||||
br label %bb.i5
|
br label %bb.i5
|
||||||
|
|
||||||
|
67
test/CodeGen/X86/twoaddr-remat.ll
Normal file
67
test/CodeGen/X86/twoaddr-remat.ll
Normal file
@ -0,0 +1,67 @@
|
|||||||
|
; RUN: llvm-as < %s | llc -march=x86 | grep 59796 | count 3
|
||||||
|
|
||||||
|
%Args = type %Value*
|
||||||
|
%Exec = type opaque*
|
||||||
|
%Identifier = type opaque*
|
||||||
|
%JSFunction = type %Value (%Exec, %Scope, %Value, %Args)
|
||||||
|
%PropertyNameArray = type opaque*
|
||||||
|
%Scope = type opaque*
|
||||||
|
%Value = type opaque*
|
||||||
|
|
||||||
|
declare i1 @X1(%Exec) readonly
|
||||||
|
|
||||||
|
declare %Value @X2(%Exec)
|
||||||
|
|
||||||
|
declare i32 @X3(%Exec, %Value)
|
||||||
|
|
||||||
|
declare %Value @X4(i32) readnone
|
||||||
|
|
||||||
|
define internal %Value @fast3bitlookup(%Exec %exec, %Scope %scope, %Value %this, %Args %args) nounwind {
|
||||||
|
prologue:
|
||||||
|
%eh_check = tail call i1 @X1( %Exec %exec ) readonly ; <i1> [#uses=1]
|
||||||
|
br i1 %eh_check, label %exception, label %no_exception
|
||||||
|
|
||||||
|
exception: ; preds = %no_exception, %prologue
|
||||||
|
%rethrow_result = tail call %Value @X2( %Exec %exec ) ; <%Value> [#uses=1]
|
||||||
|
ret %Value %rethrow_result
|
||||||
|
|
||||||
|
no_exception: ; preds = %prologue
|
||||||
|
%args_intptr = bitcast %Args %args to i32* ; <i32*> [#uses=1]
|
||||||
|
%argc_val = load i32* %args_intptr ; <i32> [#uses=1]
|
||||||
|
%cmpParamArgc = icmp sgt i32 %argc_val, 0 ; <i1> [#uses=1]
|
||||||
|
%arg_ptr = getelementptr %Args %args, i32 1 ; <%Args> [#uses=1]
|
||||||
|
%arg_val = load %Args %arg_ptr ; <%Value> [#uses=1]
|
||||||
|
%ext_arg_val = select i1 %cmpParamArgc, %Value %arg_val, %Value inttoptr (i32 5 to %Value) ; <%Value> [#uses=1]
|
||||||
|
%toInt325 = tail call i32 @X3( %Exec %exec, %Value %ext_arg_val ) ; <i32> [#uses=3]
|
||||||
|
%eh_check6 = tail call i1 @X1( %Exec %exec ) readonly ; <i1> [#uses=1]
|
||||||
|
br i1 %eh_check6, label %exception, label %no_exception7
|
||||||
|
|
||||||
|
no_exception7: ; preds = %no_exception
|
||||||
|
%shl_tmp_result = shl i32 %toInt325, 1 ; <i32> [#uses=1]
|
||||||
|
%rhs_masked13 = and i32 %shl_tmp_result, 14 ; <i32> [#uses=1]
|
||||||
|
%ashr_tmp_result = lshr i32 59796, %rhs_masked13 ; <i32> [#uses=1]
|
||||||
|
%and_tmp_result15 = and i32 %ashr_tmp_result, 3 ; <i32> [#uses=1]
|
||||||
|
%ashr_tmp_result3283 = lshr i32 %toInt325, 2 ; <i32> [#uses=1]
|
||||||
|
%rhs_masked38 = and i32 %ashr_tmp_result3283, 14 ; <i32> [#uses=1]
|
||||||
|
%ashr_tmp_result39 = lshr i32 59796, %rhs_masked38 ; <i32> [#uses=1]
|
||||||
|
%and_tmp_result41 = and i32 %ashr_tmp_result39, 3 ; <i32> [#uses=1]
|
||||||
|
%addconv = add i32 %and_tmp_result15, %and_tmp_result41 ; <i32> [#uses=1]
|
||||||
|
%ashr_tmp_result6181 = lshr i32 %toInt325, 5 ; <i32> [#uses=1]
|
||||||
|
%rhs_masked67 = and i32 %ashr_tmp_result6181, 6 ; <i32> [#uses=1]
|
||||||
|
%ashr_tmp_result68 = lshr i32 59796, %rhs_masked67 ; <i32> [#uses=1]
|
||||||
|
%and_tmp_result70 = and i32 %ashr_tmp_result68, 3 ; <i32> [#uses=1]
|
||||||
|
%addconv82 = add i32 %addconv, %and_tmp_result70 ; <i32> [#uses=3]
|
||||||
|
%rangetmp = add i32 %addconv82, 536870912 ; <i32> [#uses=1]
|
||||||
|
%rangecmp = icmp ult i32 %rangetmp, 1073741824 ; <i1> [#uses=1]
|
||||||
|
br i1 %rangecmp, label %NumberLiteralIntFast, label %NumberLiteralIntSlow
|
||||||
|
|
||||||
|
NumberLiteralIntFast: ; preds = %no_exception7
|
||||||
|
%imm_shift = shl i32 %addconv82, 2 ; <i32> [#uses=1]
|
||||||
|
%imm_or = or i32 %imm_shift, 3 ; <i32> [#uses=1]
|
||||||
|
%imm_val = inttoptr i32 %imm_or to %Value ; <%Value> [#uses=1]
|
||||||
|
ret %Value %imm_val
|
||||||
|
|
||||||
|
NumberLiteralIntSlow: ; preds = %no_exception7
|
||||||
|
%toVal = call %Value @X4( i32 %addconv82 ) ; <%Value> [#uses=1]
|
||||||
|
ret %Value %toVal
|
||||||
|
}
|
Loading…
Reference in New Issue
Block a user