mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-22 10:29:35 +00:00
[Hexagon] Adding newvalue compare and jumps.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225015 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -1369,7 +1369,8 @@ def S2_storerinew_pr : T_StorePI_RegNV<"memw", 0b10, WordAccess>;
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// operands.
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// operands.
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 11 in
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let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 11,
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opExtentAlign = 2 in
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class NVJrr_template<string mnemonic, bits<3> majOp, bit NvOpNum,
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class NVJrr_template<string mnemonic, bits<3> majOp, bit NvOpNum,
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bit isNegCond, bit isTak>
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bit isNegCond, bit isTak>
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: NVInst_V4<(outs),
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: NVInst_V4<(outs),
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@ -1377,8 +1378,7 @@ class NVJrr_template<string mnemonic, bits<3> majOp, bit NvOpNum,
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"if ("#!if(isNegCond, "!","")#mnemonic#
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"if ("#!if(isNegCond, "!","")#mnemonic#
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"($src1"#!if(!eq(NvOpNum, 0),".new, ",", ")#
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"($src1"#!if(!eq(NvOpNum, 0),".new, ",", ")#
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"$src2"#!if(!eq(NvOpNum, 1),".new))","))")#" jump:"
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"$src2"#!if(!eq(NvOpNum, 1),".new))","))")#" jump:"
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#!if(isTak, "t","nt")#" $offset",
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#!if(isTak, "t","nt")#" $offset", []> {
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[]>, Requires<[HasV4T]> {
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bits<5> src1;
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bits<5> src1;
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bits<5> src2;
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bits<5> src2;
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@ -1387,8 +1387,8 @@ class NVJrr_template<string mnemonic, bits<3> majOp, bit NvOpNum,
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bits<11> offset;
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bits<11> offset;
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let isTaken = isTak;
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let isTaken = isTak;
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let isBrTaken = !if(isTaken, "true", "false");
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let isPredicatedFalse = isNegCond;
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let isPredicatedFalse = isNegCond;
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let opNewValue{0} = NvOpNum;
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let Ns = !if(!eq(NvOpNum, 0), src1{2-0}, src2{2-0});
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let Ns = !if(!eq(NvOpNum, 0), src1{2-0}, src2{2-0});
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let RegOp = !if(!eq(NvOpNum, 0), src2, src1);
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let RegOp = !if(!eq(NvOpNum, 0), src2, src1);
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@ -1431,7 +1431,8 @@ multiclass NVJrr_base<string mnemonic, string BaseOp, bits<3> majOp,
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// if ([!]cmp.gtu(Rt,Ns.new)) jump:[n]t #r9:2
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// if ([!]cmp.gtu(Rt,Ns.new)) jump:[n]t #r9:2
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let isPredicated = 1, isBranch = 1, isNewValue = 1, isTerminator = 1,
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let isPredicated = 1, isBranch = 1, isNewValue = 1, isTerminator = 1,
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Defs = [PC], hasSideEffects = 0, validSubTargets = HasV4SubT in {
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Defs = [PC], hasSideEffects = 0, validSubTargets = HasV4SubT,
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isCodeGenOnly = 0 in {
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defm CMPEQrr : NVJrr_base<"cmp.eq", "CMPEQ", 0b000, 0>, PredRel;
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defm CMPEQrr : NVJrr_base<"cmp.eq", "CMPEQ", 0b000, 0>, PredRel;
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defm CMPGTrr : NVJrr_base<"cmp.gt", "CMPGT", 0b001, 0>, PredRel;
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defm CMPGTrr : NVJrr_base<"cmp.gt", "CMPGT", 0b001, 0>, PredRel;
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defm CMPGTUrr : NVJrr_base<"cmp.gtu", "CMPGTU", 0b010, 0>, PredRel;
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defm CMPGTUrr : NVJrr_base<"cmp.gtu", "CMPGTU", 0b010, 0>, PredRel;
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@ -1444,18 +1445,18 @@ let isPredicated = 1, isBranch = 1, isNewValue = 1, isTerminator = 1,
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// with a register and an unsigned immediate (U5) operand.
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// with a register and an unsigned immediate (U5) operand.
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 11 in
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let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 11,
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opExtentAlign = 2 in
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class NVJri_template<string mnemonic, bits<3> majOp, bit isNegCond,
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class NVJri_template<string mnemonic, bits<3> majOp, bit isNegCond,
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bit isTak>
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bit isTak>
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: NVInst_V4<(outs),
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: NVInst_V4<(outs),
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(ins IntRegs:$src1, u5Imm:$src2, brtarget:$offset),
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(ins IntRegs:$src1, u5Imm:$src2, brtarget:$offset),
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"if ("#!if(isNegCond, "!","")#mnemonic#"($src1.new, #$src2)) jump:"
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"if ("#!if(isNegCond, "!","")#mnemonic#"($src1.new, #$src2)) jump:"
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#!if(isTak, "t","nt")#" $offset",
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#!if(isTak, "t","nt")#" $offset", []> {
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[]>, Requires<[HasV4T]> {
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let isTaken = isTak;
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let isTaken = isTak;
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let isPredicatedFalse = isNegCond;
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let isPredicatedFalse = isNegCond;
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let isBrTaken = !if(isTaken, "true", "false");
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let isTaken = isTak;
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bits<3> src1;
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bits<3> src1;
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bits<5> src2;
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bits<5> src2;
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@ -1491,7 +1492,8 @@ multiclass NVJri_base<string mnemonic, string BaseOp, bits<3> majOp> {
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// if ([!]cmp.gtu(Ns.new,#U5)) jump:[n]t #r9:2
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// if ([!]cmp.gtu(Ns.new,#U5)) jump:[n]t #r9:2
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let isPredicated = 1, isBranch = 1, isNewValue = 1, isTerminator = 1,
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let isPredicated = 1, isBranch = 1, isNewValue = 1, isTerminator = 1,
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Defs = [PC], hasSideEffects = 0, validSubTargets = HasV4SubT in {
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Defs = [PC], hasSideEffects = 0, validSubTargets = HasV4SubT,
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isCodeGenOnly = 0 in {
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defm CMPEQri : NVJri_base<"cmp.eq", "CMPEQ", 0b000>, PredRel;
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defm CMPEQri : NVJri_base<"cmp.eq", "CMPEQ", 0b000>, PredRel;
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defm CMPGTri : NVJri_base<"cmp.gt", "CMPGT", 0b001>, PredRel;
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defm CMPGTri : NVJri_base<"cmp.gt", "CMPGT", 0b001>, PredRel;
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defm CMPGTUri : NVJri_base<"cmp.gtu", "CMPGTU", 0b010>, PredRel;
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defm CMPGTUri : NVJri_base<"cmp.gtu", "CMPGTU", 0b010>, PredRel;
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@ -1502,19 +1504,19 @@ let isPredicated = 1, isBranch = 1, isNewValue = 1, isTerminator = 1,
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// with a register and an hardcoded 0/-1 immediate value.
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// with a register and an hardcoded 0/-1 immediate value.
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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let isExtendable = 1, opExtendable = 1, isExtentSigned = 1, opExtentBits = 11 in
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let isExtendable = 1, opExtendable = 1, isExtentSigned = 1, opExtentBits = 11,
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opExtentAlign = 2 in
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class NVJ_ConstImm_template<string mnemonic, bits<3> majOp, string ImmVal,
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class NVJ_ConstImm_template<string mnemonic, bits<3> majOp, string ImmVal,
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bit isNegCond, bit isTak>
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bit isNegCond, bit isTak>
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: NVInst_V4<(outs),
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: NVInst_V4<(outs),
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(ins IntRegs:$src1, brtarget:$offset),
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(ins IntRegs:$src1, brtarget:$offset),
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"if ("#!if(isNegCond, "!","")#mnemonic
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"if ("#!if(isNegCond, "!","")#mnemonic
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#"($src1.new, #"#ImmVal#")) jump:"
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#"($src1.new, #"#ImmVal#")) jump:"
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#!if(isTak, "t","nt")#" $offset",
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#!if(isTak, "t","nt")#" $offset", []> {
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[]>, Requires<[HasV4T]> {
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let isTaken = isTak;
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let isTaken = isTak;
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let isPredicatedFalse = isNegCond;
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let isPredicatedFalse = isNegCond;
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let isBrTaken = !if(isTaken, "true", "false");
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let isTaken = isTak;
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bits<3> src1;
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bits<3> src1;
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bits<11> offset;
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bits<11> offset;
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@ -1539,8 +1541,8 @@ multiclass NVJ_ConstImm_cond<string mnemonic, bits<3> majOp, string ImmVal,
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multiclass NVJ_ConstImm_base<string mnemonic, string BaseOp, bits<3> majOp,
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multiclass NVJ_ConstImm_base<string mnemonic, string BaseOp, bits<3> majOp,
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string ImmVal> {
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string ImmVal> {
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let BaseOpcode = BaseOp#_NVJ_ConstImm in {
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let BaseOpcode = BaseOp#_NVJ_ConstImm in {
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defm _t_Jumpnv : NVJ_ConstImm_cond<mnemonic, majOp, ImmVal, 0>; // True cond
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defm _t_Jumpnv : NVJ_ConstImm_cond<mnemonic, majOp, ImmVal, 0>; // True
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defm _f_Jumpnv : NVJ_ConstImm_cond<mnemonic, majOp, ImmVal, 1>; // False Cond
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defm _f_Jumpnv : NVJ_ConstImm_cond<mnemonic, majOp, ImmVal, 1>; // False
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}
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}
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}
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}
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@ -1549,12 +1551,28 @@ multiclass NVJ_ConstImm_base<string mnemonic, string BaseOp, bits<3> majOp,
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// if ([!]cmp.gt(Ns.new,#-1)) jump:[n]t #r9:2
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// if ([!]cmp.gt(Ns.new,#-1)) jump:[n]t #r9:2
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let isPredicated = 1, isBranch = 1, isNewValue = 1, isTerminator=1,
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let isPredicated = 1, isBranch = 1, isNewValue = 1, isTerminator=1,
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Defs = [PC], hasSideEffects = 0 in {
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Defs = [PC], hasSideEffects = 0, isCodeGenOnly = 0 in {
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defm TSTBIT0 : NVJ_ConstImm_base<"tstbit", "TSTBIT", 0b011, "0">, PredRel;
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defm TSTBIT0 : NVJ_ConstImm_base<"tstbit", "TSTBIT", 0b011, "0">, PredRel;
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defm CMPEQn1 : NVJ_ConstImm_base<"cmp.eq", "CMPEQ", 0b100, "-1">, PredRel;
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defm CMPEQn1 : NVJ_ConstImm_base<"cmp.eq", "CMPEQ", 0b100, "-1">, PredRel;
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defm CMPGTn1 : NVJ_ConstImm_base<"cmp.gt", "CMPGT", 0b101, "-1">, PredRel;
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defm CMPGTn1 : NVJ_ConstImm_base<"cmp.gt", "CMPGT", 0b101, "-1">, PredRel;
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}
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}
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// J4_hintjumpr: Hint indirect conditional jump.
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let isBranch = 1, isIndirectBranch = 1, hasSideEffects = 0, isCodeGenOnly = 0 in
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def J4_hintjumpr: JRInst <
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(outs),
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(ins IntRegs:$Rs),
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"hintjr($Rs)"> {
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bits<5> Rs;
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let IClass = 0b0101;
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let Inst{27-21} = 0b0010101;
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let Inst{20-16} = Rs;
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}
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//===----------------------------------------------------------------------===//
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// NV/J -
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// XTYPE/ALU +
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// XTYPE/ALU +
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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134
test/MC/Disassembler/Hexagon/nv_j.txt
Normal file
134
test/MC/Disassembler/Hexagon/nv_j.txt
Normal file
@ -0,0 +1,134 @@
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# RUN: llvm-mc --triple hexagon -disassemble < %s | FileCheck %s
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0x11 0x40 0x71 0x70 0x92 0xd5 0x02 0x20
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# CHECK: r17 = r17
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# CHECK-NEXT: if (cmp.eq(r2.new, r21)) jump:nt
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0x11 0x40 0x71 0x70 0x92 0xf5 0x02 0x20
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# CHECK: r17 = r17
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# CHECK-NEXT: if (cmp.eq(r2.new, r21)) jump:t
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0x11 0x40 0x71 0x70 0x92 0xd5 0x42 0x20
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# CHECK: r17 = r17
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# CHECK-NEXT: if (!cmp.eq(r2.new, r21)) jump:nt
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0x11 0x40 0x71 0x70 0x92 0xf5 0x42 0x20
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# CHECK: r17 = r17
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# CHECK-NEXT: if (!cmp.eq(r2.new, r21)) jump:t
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0x11 0x40 0x71 0x70 0x92 0xd5 0x82 0x20
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# CHECK: r17 = r17
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# CHECK-NEXT: if (cmp.gt(r2.new, r21)) jump:nt
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0x11 0x40 0x71 0x70 0x92 0xf5 0x82 0x20
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# CHECK: r17 = r17
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# CHECK-NEXT: if (cmp.gt(r2.new, r21)) jump:t
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0x11 0x40 0x71 0x70 0x92 0xd5 0xc2 0x20
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# CHECK: r17 = r17
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# CHECK-NEXT: if (!cmp.gt(r2.new, r21)) jump:nt
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0x11 0x40 0x71 0x70 0x92 0xf5 0xc2 0x20
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# CHECK: r17 = r17
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# CHECK-NEXT: if (!cmp.gt(r2.new, r21)) jump:t
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0x11 0x40 0x71 0x70 0x92 0xd5 0x02 0x21
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# CHECK: r17 = r17
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# CHECK-NEXT: if (cmp.gtu(r2.new, r21)) jump:nt
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0x11 0x40 0x71 0x70 0x92 0xf5 0x02 0x21
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# CHECK: r17 = r17
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# CHECK-NEXT: if (cmp.gtu(r2.new, r21)) jump:t
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0x11 0x40 0x71 0x70 0x92 0xd5 0x42 0x21
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# CHECK: r17 = r17
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# CHECK-NEXT: if (!cmp.gtu(r2.new, r21)) jump:nt
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0x11 0x40 0x71 0x70 0x92 0xf5 0x42 0x21
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# CHECK: r17 = r17
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# CHECK-NEXT: if (!cmp.gtu(r2.new, r21)) jump:t
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0x11 0x40 0x71 0x70 0x92 0xd5 0x82 0x21
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# CHECK: r17 = r17
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# CHECK-NEXT: if (cmp.gt(r21, r2.new)) jump:nt
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0x11 0x40 0x71 0x70 0x92 0xf5 0x82 0x21
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# CHECK: r17 = r17
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# CHECK-NEXT: if (cmp.gt(r21, r2.new)) jump:t
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0x11 0x40 0x71 0x70 0x92 0xd5 0xc2 0x21
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# CHECK: r17 = r17
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# CHECK-NEXT: if (!cmp.gt(r21, r2.new)) jump:nt
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0x11 0x40 0x71 0x70 0x92 0xf5 0xc2 0x21
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# CHECK: r17 = r17
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# CHECK-NEXT: if (!cmp.gt(r21, r2.new)) jump:t
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0x11 0x40 0x71 0x70 0x92 0xd5 0x02 0x22
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# CHECK: r17 = r17
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# CHECK-NEXT: if (cmp.gtu(r21, r2.new)) jump:nt
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0x11 0x40 0x71 0x70 0x92 0xf5 0x02 0x22
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# CHECK: r17 = r17
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# CHECK-NEXT: if (cmp.gtu(r21, r2.new)) jump:t
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0x11 0x40 0x71 0x70 0x92 0xd5 0x42 0x22
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# CHECK: r17 = r17
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# CHECK-NEXT: if (!cmp.gtu(r21, r2.new)) jump:nt
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0x11 0x40 0x71 0x70 0x92 0xf5 0x42 0x22
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# CHECK: r17 = r17
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# CHECK-NEXT: if (!cmp.gtu(r21, r2.new)) jump:t
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0x11 0x40 0x71 0x70 0x92 0xd5 0x02 0x24
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# CHECK: r17 = r17
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# CHECK-NEXT: if (cmp.eq(r2.new, #21)) jump:nt
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0x11 0x40 0x71 0x70 0x92 0xf5 0x02 0x24
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# CHECK: r17 = r17
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# CHECK-NETX: if (cmp.eq(r2.new, #21)) jump:t
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0x11 0x40 0x71 0x70 0x92 0xd5 0x42 0x24
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# CHECK: r17 = r17
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# CHECK-NEXT: if (!cmp.eq(r2.new, #21)) jump:nt
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0x11 0x40 0x71 0x70 0x92 0xf5 0x42 0x24
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# CHECK: r17 = r17
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# CHECK-NEXT: if (!cmp.eq(r2.new, #21)) jump:t
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0x11 0x40 0x71 0x70 0x92 0xd5 0x82 0x24
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# CHECK: r17 = r17
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# CHECK-NEXT: if (cmp.gt(r2.new, #21)) jump:nt
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0x11 0x40 0x71 0x70 0x92 0xf5 0x82 0x24
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# CHECK: r17 = r17
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# CHECK-NEXT: if (cmp.gt(r2.new, #21)) jump:t
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0x11 0x40 0x71 0x70 0x92 0xd5 0xc2 0x24
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# CHECK: r17 = r17
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# CHECK-NEXT: if (!cmp.gt(r2.new, #21)) jump:nt
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0x11 0x40 0x71 0x70 0x92 0xf5 0xc2 0x24
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# CHECK: r17 = r17
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# CHECK-NEXT: if (!cmp.gt(r2.new, #21)) jump:t
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0x11 0x40 0x71 0x70 0x92 0xd5 0x02 0x25
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# CHECK: r17 = r17
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# CHECK-NEXT: if (cmp.gtu(r2.new, #21)) jump:nt
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0x11 0x40 0x71 0x70 0x92 0xf5 0x02 0x25
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# CHECK: r17 = r17
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# CHECK-NEXT: if (cmp.gtu(r2.new, #21)) jump:t
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0x11 0x40 0x71 0x70 0x92 0xd5 0x42 0x25
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# CHECK: r17 = r17
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# CHECK-NEXT: if (!cmp.gtu(r2.new, #21)) jump:nt
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0x11 0x40 0x71 0x70 0x92 0xf5 0x42 0x25
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# CHECK: r17 = r17
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# CHECK-NEXT: if (!cmp.gtu(r2.new, #21)) jump:t
|
||||||
|
0x11 0x40 0x71 0x70 0x92 0xc0 0x82 0x25
|
||||||
|
# CHECK: r17 = r17
|
||||||
|
# CHECK-NEXT: if (tstbit(r2.new, #0)) jump:nt
|
||||||
|
0x11 0x40 0x71 0x70 0x92 0xe0 0x82 0x25
|
||||||
|
# CHECK: r17 = r17
|
||||||
|
# CHECK-NEXT: if (tstbit(r2.new, #0)) jump:t
|
||||||
|
0x11 0x40 0x71 0x70 0x92 0xc0 0xc2 0x25
|
||||||
|
# CHECK: r17 = r17
|
||||||
|
# CHECK-NEXT: if (!tstbit(r2.new, #0)) jump:nt
|
||||||
|
0x11 0x40 0x71 0x70 0x92 0xe0 0xc2 0x25
|
||||||
|
# CHECK: r17 = r17
|
||||||
|
# CHECK-NEXT: if (!tstbit(r2.new, #0)) jump:t
|
||||||
|
0x11 0x40 0x71 0x70 0x92 0xc0 0x02 0x26
|
||||||
|
# CHECK: r17 = r17
|
||||||
|
# CHECK-NEXT: if (cmp.eq(r2.new, #-1)) jump:nt
|
||||||
|
0x11 0x40 0x71 0x70 0x92 0xe0 0x02 0x26
|
||||||
|
# CHECK: r17 = r17
|
||||||
|
# CHECK-NEXT: if (cmp.eq(r2.new, #-1)) jump:t
|
||||||
|
0x11 0x40 0x71 0x70 0x92 0xc0 0x42 0x26
|
||||||
|
# CHECK: r17 = r17
|
||||||
|
# CHECK-NEXT: if (!cmp.eq(r2.new, #-1)) jump:nt
|
||||||
|
0x11 0x40 0x71 0x70 0x92 0xe0 0x42 0x26
|
||||||
|
# CHECK: r17 = r17
|
||||||
|
# CHECK-NEXT: if (!cmp.eq(r2.new, #-1)) jump:t
|
||||||
|
0x11 0x40 0x71 0x70 0x92 0xc0 0x82 0x26
|
||||||
|
# CHECK: r17 = r17
|
||||||
|
# CHECK-NEXT: if (cmp.gt(r2.new, #-1)) jump:nt
|
||||||
|
0x11 0x40 0x71 0x70 0x92 0xe0 0x82 0x26
|
||||||
|
# CHECK: r17 = r17
|
||||||
|
# CHECK-NEXT: if (cmp.gt(r2.new, #-1)) jump:t
|
||||||
|
0x11 0x40 0x71 0x70 0x92 0xc0 0xc2 0x26
|
||||||
|
# CHECK: r17 = r17
|
||||||
|
# CHECK-NEXT: if (!cmp.gt(r2.new, #-1)) jump:nt
|
||||||
|
0x11 0x40 0x71 0x70 0x92 0xe0 0xc2 0x26
|
||||||
|
# CHECK: r17 = r17
|
||||||
|
# CHECK-NEXT: if (!cmp.gt(r2.new, #-1)) jump:t
|
Loading…
Reference in New Issue
Block a user