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https://github.com/c64scene-ar/llvm-6502.git
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Tidy up a bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145458 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -78,6 +78,7 @@ def VectorIndex32 : Operand<i32>, ImmLeaf<i32, [{
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def VecListOneDAsmOperand : AsmOperandClass {
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let Name = "VecListOneD";
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let ParserMethod = "parseVectorList";
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let RenderMethod = "addVecListOperands";
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}
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def VecListOneD : RegisterOperand<DPR, "printVectorListOne"> {
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let ParserMatchClass = VecListOneDAsmOperand;
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@ -86,6 +87,7 @@ def VecListOneD : RegisterOperand<DPR, "printVectorListOne"> {
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def VecListTwoDAsmOperand : AsmOperandClass {
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let Name = "VecListTwoD";
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let ParserMethod = "parseVectorList";
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let RenderMethod = "addVecListOperands";
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}
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def VecListTwoD : RegisterOperand<DPR, "printVectorListTwo"> {
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let ParserMatchClass = VecListTwoDAsmOperand;
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@ -94,6 +96,7 @@ def VecListTwoD : RegisterOperand<DPR, "printVectorListTwo"> {
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def VecListThreeDAsmOperand : AsmOperandClass {
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let Name = "VecListThreeD";
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let ParserMethod = "parseVectorList";
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let RenderMethod = "addVecListOperands";
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}
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def VecListThreeD : RegisterOperand<DPR, "printVectorListThree"> {
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let ParserMatchClass = VecListThreeDAsmOperand;
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@ -102,6 +105,7 @@ def VecListThreeD : RegisterOperand<DPR, "printVectorListThree"> {
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def VecListFourDAsmOperand : AsmOperandClass {
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let Name = "VecListFourD";
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let ParserMethod = "parseVectorList";
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let RenderMethod = "addVecListOperands";
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}
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def VecListFourD : RegisterOperand<DPR, "printVectorListFour"> {
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let ParserMatchClass = VecListFourDAsmOperand;
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@ -110,6 +114,7 @@ def VecListFourD : RegisterOperand<DPR, "printVectorListFour"> {
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def VecListTwoQAsmOperand : AsmOperandClass {
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let Name = "VecListTwoQ";
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let ParserMethod = "parseVectorList";
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let RenderMethod = "addVecListOperands";
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}
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def VecListTwoQ : RegisterOperand<DPR, "printVectorListTwo"> {
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let ParserMatchClass = VecListTwoQAsmOperand;
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@ -1527,39 +1527,11 @@ public:
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Inst.addOperand(MCOperand::CreateImm(unsigned(getProcIFlags())));
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}
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void addVecListOneDOperands(MCInst &Inst, unsigned N) const {
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void addVecListOperands(MCInst &Inst, unsigned N) const {
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assert(N == 1 && "Invalid number of operands!");
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Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum));
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}
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void addVecListTwoDOperands(MCInst &Inst, unsigned N) const {
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assert(N == 1 && "Invalid number of operands!");
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// Only the first register actually goes on the instruction. The rest
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// are implied by the opcode.
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Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum));
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}
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void addVecListThreeDOperands(MCInst &Inst, unsigned N) const {
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assert(N == 1 && "Invalid number of operands!");
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// Only the first register actually goes on the instruction. The rest
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// are implied by the opcode.
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Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum));
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}
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void addVecListFourDOperands(MCInst &Inst, unsigned N) const {
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assert(N == 1 && "Invalid number of operands!");
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// Only the first register actually goes on the instruction. The rest
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// are implied by the opcode.
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Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum));
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}
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void addVecListTwoQOperands(MCInst &Inst, unsigned N) const {
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assert(N == 1 && "Invalid number of operands!");
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// Only the first register actually goes on the instruction. The rest
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// are implied by the opcode.
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Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum));
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}
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void addVectorIndex8Operands(MCInst &Inst, unsigned N) const {
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assert(N == 1 && "Invalid number of operands!");
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Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
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@ -3444,7 +3416,7 @@ bool ARMAsmParser::
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cvtVLDwbFixed(MCInst &Inst, unsigned Opcode,
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const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
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// Vd
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((ARMOperand*)Operands[3])->addVecListTwoDOperands(Inst, 1);
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((ARMOperand*)Operands[3])->addVecListOperands(Inst, 1);
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// Create a writeback register dummy placeholder.
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Inst.addOperand(MCOperand::CreateImm(0));
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// Vn
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@ -3458,7 +3430,7 @@ bool ARMAsmParser::
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cvtVLDwbRegister(MCInst &Inst, unsigned Opcode,
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const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
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// Vd
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((ARMOperand*)Operands[3])->addVecListTwoDOperands(Inst, 1);
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((ARMOperand*)Operands[3])->addVecListOperands(Inst, 1);
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// Create a writeback register dummy placeholder.
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Inst.addOperand(MCOperand::CreateImm(0));
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// Vn
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@ -3478,7 +3450,7 @@ cvtVSTwbFixed(MCInst &Inst, unsigned Opcode,
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// Vn
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((ARMOperand*)Operands[4])->addAlignedMemoryOperands(Inst, 2);
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// Vt
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((ARMOperand*)Operands[3])->addVecListTwoDOperands(Inst, 1);
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((ARMOperand*)Operands[3])->addVecListOperands(Inst, 1);
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// pred
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((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
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return true;
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@ -3494,7 +3466,7 @@ cvtVSTwbRegister(MCInst &Inst, unsigned Opcode,
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// Vm
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((ARMOperand*)Operands[5])->addRegOperands(Inst, 1);
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// Vt
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((ARMOperand*)Operands[3])->addVecListTwoDOperands(Inst, 1);
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((ARMOperand*)Operands[3])->addVecListOperands(Inst, 1);
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// pred
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((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
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return true;
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