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Have MachineFunction cache a pointer to the subtarget to make lookups

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shorter/easier and have the DAG use that to do the same lookup. This
can be used in the future for TargetMachine based caching lookups from
the MachineFunction easily.

Update the MIPS subtarget switching machinery to update this pointer
at the same time it runs.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214838 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Eric Christopher
2014-08-05 02:39:49 +00:00
parent c2328d552c
commit 6035518e3b
136 changed files with 491 additions and 739 deletions
Download Patch File Download Diff File Expand all files Collapse all files

24
lib/Target/XCore/XCoreFrameLowering.cpp
View File

@@ -227,8 +227,7 @@ void XCoreFrameLowering::emitPrologue(MachineFunction &MF) const {
MachineModuleInfo *MMI = &MF.getMMI();
const MCRegisterInfo *MRI = MMI->getContext().getRegisterInfo();
const XCoreInstrInfo &TII =
*static_cast<const XCoreInstrInfo *>(
MF.getTarget().getSubtargetImpl()->getInstrInfo());
*static_cast<const XCoreInstrInfo *>(MF.getSubtarget().getInstrInfo());
XCoreFunctionInfo *XFI = MF.getInfo<XCoreFunctionInfo>();
// Debug location must be unknown since the first debug location is used
// to determine the end of the prologue.
@@ -264,8 +263,8 @@ void XCoreFrameLowering::emitPrologue(MachineFunction &MF) const {
MBB.addLiveIn(XCore::LR);
MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(Opcode));
MIB.addImm(Adjusted);
MIB->addRegisterKilled(
XCore::LR, MF.getTarget().getSubtargetImpl()->getRegisterInfo(), true);
MIB->addRegisterKilled(XCore::LR, MF.getSubtarget().getRegisterInfo(),
true);
if (emitFrameMoves) {
EmitDefCfaOffset(MBB, MBBI, dl, TII, MMI, Adjusted*4);
unsigned DRegNum = MRI->getDwarfRegNum(XCore::LR, true);
@@ -327,7 +326,7 @@ void XCoreFrameLowering::emitPrologue(MachineFunction &MF) const {
// We do not save/spill these registers.
SmallVector<StackSlotInfo,2> SpillList;
GetEHSpillList(SpillList, MFI, XFI,
MF.getTarget().getSubtargetImpl()->getTargetLowering());
MF.getSubtarget().getTargetLowering());
assert(SpillList.size()==2 && "Unexpected SpillList size");
EmitCfiOffset(MBB, MBBI, dl, TII, MMI,
MRI->getDwarfRegNum(SpillList[0].Reg, true),
@@ -344,8 +343,7 @@ void XCoreFrameLowering::emitEpilogue(MachineFunction &MF,
MachineFrameInfo *MFI = MF.getFrameInfo();
MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
const XCoreInstrInfo &TII =
*static_cast<const XCoreInstrInfo *>(
MF.getTarget().getSubtargetImpl()->getInstrInfo());
*static_cast<const XCoreInstrInfo *>(MF.getSubtarget().getInstrInfo());
XCoreFunctionInfo *XFI = MF.getInfo<XCoreFunctionInfo>();
DebugLoc dl = MBBI->getDebugLoc();
unsigned RetOpcode = MBBI->getOpcode();
@@ -360,8 +358,7 @@ void XCoreFrameLowering::emitEpilogue(MachineFunction &MF,
// 'Restore' the exception info the unwinder has placed into the stack
// slots.
SmallVector<StackSlotInfo,2> SpillList;
GetEHSpillList(SpillList, MFI, XFI,
MF.getTarget().getSubtargetImpl()->getTargetLowering());
GetEHSpillList(SpillList, MFI, XFI, MF.getSubtarget().getTargetLowering());
RestoreSpillList(MBB, MBBI, dl, TII, RemainingAdj, SpillList);
// Return to the landing pad.
@@ -419,8 +416,7 @@ spillCalleeSavedRegisters(MachineBasicBlock &MBB,
return true;
MachineFunction *MF = MBB.getParent();
const TargetInstrInfo &TII =
*MF->getTarget().getSubtargetImpl()->getInstrInfo();
const TargetInstrInfo &TII = *MF->getSubtarget().getInstrInfo();
XCoreFunctionInfo *XFI = MF->getInfo<XCoreFunctionInfo>();
bool emitFrameMoves = XCoreRegisterInfo::needsFrameMoves(*MF);
@@ -453,8 +449,7 @@ restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
const std::vector<CalleeSavedInfo> &CSI,
const TargetRegisterInfo *TRI) const{
MachineFunction *MF = MBB.getParent();
const TargetInstrInfo &TII =
*MF->getTarget().getSubtargetImpl()->getInstrInfo();
const TargetInstrInfo &TII = *MF->getSubtarget().getInstrInfo();
bool AtStart = MI == MBB.begin();
MachineBasicBlock::iterator BeforeI = MI;
if (!AtStart)
@@ -487,8 +482,7 @@ void XCoreFrameLowering::
eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
MachineBasicBlock::iterator I) const {
const XCoreInstrInfo &TII =
*static_cast<const XCoreInstrInfo *>(
MF.getTarget().getSubtargetImpl()->getInstrInfo());
*static_cast<const XCoreInstrInfo *>(MF.getSubtarget().getInstrInfo());
if (!hasReservedCallFrame(MF)) {
// Turn the adjcallstackdown instruction into 'extsp <amt>' and the
// adjcallstackup instruction into 'ldaw sp, sp[<amt>]'

3
lib/Target/XCore/XCoreFrameToArgsOffsetElim.cpp
View File

@@ -44,8 +44,7 @@ FunctionPass *llvm::createXCoreFrameToArgsOffsetEliminationPass() {
bool XCoreFTAOElim::runOnMachineFunction(MachineFunction &MF) {
const XCoreInstrInfo &TII =
*static_cast<const XCoreInstrInfo *>(
MF.getTarget().getSubtargetImpl()->getInstrInfo());
*static_cast<const XCoreInstrInfo *>(MF.getSubtarget().getInstrInfo());
unsigned StackSize = MF.getFrameInfo()->getStackSize();
for (MachineFunction::iterator MFI = MF.begin(), E = MF.end(); MFI != E;
++MFI) {

15
lib/Target/XCore/XCoreRegisterInfo.cpp
View File

@@ -222,8 +222,7 @@ const MCPhysReg* XCoreRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF
XCore::R8, XCore::R9,
0
};
const TargetFrameLowering *TFI =
MF->getTarget().getSubtargetImpl()->getFrameLowering();
const TargetFrameLowering *TFI = MF->getSubtarget().getFrameLowering();
if (TFI->hasFP(*MF))
return CalleeSavedRegsFP;
return CalleeSavedRegs;
@@ -231,8 +230,7 @@ const MCPhysReg* XCoreRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF
BitVector XCoreRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
BitVector Reserved(getNumRegs());
const TargetFrameLowering *TFI =
MF.getTarget().getSubtargetImpl()->getFrameLowering();
const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering();
Reserved.set(XCore::CP);
Reserved.set(XCore::DP);
@@ -270,11 +268,9 @@ XCoreRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
MachineFunction &MF = *MI.getParent()->getParent();
const XCoreInstrInfo &TII =
*static_cast<const XCoreInstrInfo *>(
MF.getTarget().getSubtargetImpl()->getInstrInfo());
*static_cast<const XCoreInstrInfo *>(MF.getSubtarget().getInstrInfo());
const TargetFrameLowering *TFI =
MF.getTarget().getSubtargetImpl()->getFrameLowering();
const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering();
int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex);
int StackSize = MF.getFrameInfo()->getStackSize();
@@ -328,8 +324,7 @@ XCoreRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
unsigned XCoreRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
const TargetFrameLowering *TFI =
MF.getTarget().getSubtargetImpl()->getFrameLowering();
const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering();
return TFI->hasFP(MF) ? XCore::R10 : XCore::SP;
}

3
lib/Target/XCore/XCoreSelectionDAGInfo.cpp
View File

@@ -33,8 +33,7 @@ EmitTargetCodeForMemcpy(SelectionDAG &DAG, SDLoc dl, SDValue Chain,
// Call __memcpy_4 if the src, dst and size are all 4 byte aligned.
if (!AlwaysInline && (Align & 3) == 0 &&
DAG.MaskedValueIsZero(Size, APInt(SizeBitWidth, 3))) {
const TargetLowering &TLI =
*DAG.getTarget().getSubtargetImpl()->getTargetLowering();
const TargetLowering &TLI = *DAG.getSubtarget().getTargetLowering();
TargetLowering::ArgListTy Args;
TargetLowering::ArgListEntry Entry;
Entry.Ty = TLI.getDataLayout()->getIntPtrType(*DAG.getContext());