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https://github.com/c64scene-ar/llvm-6502.git
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[ARM] Combine base-updating/post-incrementing vector load/stores.
We used to only combine intrinsics, and turn them into VLD1_UPD/VST1_UPD when the base pointer is incremented after the load/store. We can do the same thing for generic load/stores. Note that we can only combine the first load/store+adds pair in a sequence (as might be generated for a v16f32 load for instance), because other combines turn the base pointer addition chain (each computing the address of the next load, from the address of the last load) into independent additions (common base pointer + this load's offset). Differential Revision: http://reviews.llvm.org/D6585 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223862 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Ahmed Bougacha
parent
3490d23337
commit
605c40341b
@ -567,6 +567,7 @@ ARMTargetLowering::ARMTargetLowering(const TargetMachine &TM)
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setTargetDAGCombine(ISD::FP_TO_SINT);
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setTargetDAGCombine(ISD::FP_TO_UINT);
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setTargetDAGCombine(ISD::FDIV);
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setTargetDAGCombine(ISD::LOAD);
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// It is legal to extload from v4i8 to v4i16 or v4i32.
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MVT Tys[6] = {MVT::v8i8, MVT::v4i8, MVT::v2i8,
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@ -8868,15 +8869,18 @@ static SDValue PerformVECTOR_SHUFFLECombine(SDNode *N, SelectionDAG &DAG) {
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DAG.getUNDEF(VT), NewMask.data());
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}
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/// CombineBaseUpdate - Target-specific DAG combine function for VLDDUP and
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/// NEON load/store intrinsics to merge base address updates.
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/// CombineBaseUpdate - Target-specific DAG combine function for VLDDUP,
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/// NEON load/store intrinsics, and generic vector load/stores, to merge
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/// base address updates.
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/// For generic load/stores, the memory type is assumed to be a vector.
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/// The caller is assumed to have checked legality.
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static SDValue CombineBaseUpdate(SDNode *N,
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TargetLowering::DAGCombinerInfo &DCI) {
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SelectionDAG &DAG = DCI.DAG;
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bool isIntrinsic = (N->getOpcode() == ISD::INTRINSIC_VOID ||
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N->getOpcode() == ISD::INTRINSIC_W_CHAIN);
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unsigned AddrOpIdx = (isIntrinsic ? 2 : 1);
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bool isStore = N->getOpcode() == ISD::STORE;
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unsigned AddrOpIdx = ((isIntrinsic || isStore) ? 2 : 1);
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SDValue Addr = N->getOperand(AddrOpIdx);
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// Search for a use of the address operand that is an increment.
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@ -8937,6 +8941,10 @@ static SDValue CombineBaseUpdate(SDNode *N,
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case ARMISD::VLD2DUP: NewOpc = ARMISD::VLD2DUP_UPD; NumVecs = 2; break;
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case ARMISD::VLD3DUP: NewOpc = ARMISD::VLD3DUP_UPD; NumVecs = 3; break;
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case ARMISD::VLD4DUP: NewOpc = ARMISD::VLD4DUP_UPD; NumVecs = 4; break;
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case ISD::LOAD: NewOpc = ARMISD::VLD1_UPD;
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NumVecs = 1; isLaneOp = false; break;
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case ISD::STORE: NewOpc = ARMISD::VST1_UPD;
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NumVecs = 1; isLoad = false; isLaneOp = false; break;
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}
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}
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@ -8944,8 +8952,11 @@ static SDValue CombineBaseUpdate(SDNode *N,
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EVT VecTy;
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if (isLoad)
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VecTy = N->getValueType(0);
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else
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else if (isIntrinsic)
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VecTy = N->getOperand(AddrOpIdx+1).getValueType();
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else
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VecTy = N->getOperand(1).getValueType();
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unsigned NumBytes = NumVecs * VecTy.getSizeInBits() / 8;
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if (isLaneOp)
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NumBytes /= VecTy.getVectorNumElements();
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@ -8978,8 +8989,13 @@ static SDValue CombineBaseUpdate(SDNode *N,
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Ops.push_back(N->getOperand(0)); // incoming chain
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Ops.push_back(N->getOperand(AddrOpIdx));
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Ops.push_back(Inc);
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for (unsigned i = AddrOpIdx + 1; i < N->getNumOperands(); ++i) {
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Ops.push_back(N->getOperand(i));
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if (StoreSDNode *StN = dyn_cast<StoreSDNode>(N)) {
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// Try to match the intrinsic's signature
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Ops.push_back(StN->getValue());
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Ops.push_back(DAG.getConstant(StN->getAlignment(), MVT::i32));
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} else {
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for (unsigned i = AddrOpIdx + 1; i < N->getNumOperands(); ++i)
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Ops.push_back(N->getOperand(i));
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}
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MemSDNode *MemInt = cast<MemSDNode>(N);
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SDValue UpdN = DAG.getMemIntrinsicNode(NewOpc, SDLoc(N), SDTys,
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@ -9121,6 +9137,17 @@ static SDValue PerformVDUPLANECombine(SDNode *N,
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return DCI.DAG.getNode(ISD::BITCAST, SDLoc(N), VT, Op);
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}
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static SDValue PerformLOADCombine(SDNode *N,
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TargetLowering::DAGCombinerInfo &DCI) {
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EVT VT = N->getValueType(0);
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// If this is a legal vector load, try to combine it into a VLD1_UPD.
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if (VT.isVector() && DCI.DAG.getTargetLoweringInfo().isTypeLegal(VT))
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return CombineBaseUpdate(N, DCI);
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return SDValue();
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}
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/// PerformSTORECombine - Target-specific dag combine xforms for
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/// ISD::STORE.
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static SDValue PerformSTORECombine(SDNode *N,
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@ -9261,6 +9288,10 @@ static SDValue PerformSTORECombine(SDNode *N,
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St->getAAInfo());
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}
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// If this is a legal vector store, try to combine it into a VST1_UPD.
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if (VT.isVector() && DCI.DAG.getTargetLoweringInfo().isTypeLegal(VT))
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return CombineBaseUpdate(N, DCI);
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return SDValue();
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}
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@ -9852,6 +9883,7 @@ SDValue ARMTargetLowering::PerformDAGCombine(SDNode *N,
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case ISD::ANY_EXTEND: return PerformExtendCombine(N, DCI.DAG, Subtarget);
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case ISD::SELECT_CC: return PerformSELECT_CCCombine(N, DCI.DAG, Subtarget);
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case ARMISD::CMOV: return PerformCMOVCombine(N, DCI.DAG);
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case ISD::LOAD: return PerformLOADCombine(N, DCI);
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case ARMISD::VLD2DUP:
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case ARMISD::VLD3DUP:
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case ARMISD::VLD4DUP:
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@ -9,8 +9,8 @@
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define void @test1(<16 x float>* noalias sret %agg.result) nounwind ssp "no-realign-stack" {
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entry:
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; NO-REALIGN-LABEL: test1
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; NO-REALIGN: vld1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R1:[0-9]+]]:128]
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; NO-REALIGN: add r[[R2:[0-9]+]], r[[R1]], #16
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; NO-REALIGN: mov r[[R2:[0-9]+]], r[[R1:[0-9]+]]
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; NO-REALIGN: vld1.32 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128]!
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; NO-REALIGN: vld1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128]
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; NO-REALIGN: add r[[R2:[0-9]+]], r[[R1]], #32
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; NO-REALIGN: vld1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128]
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@ -21,16 +21,14 @@ entry:
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; NO-REALIGN: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128]
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; NO-REALIGN: add r[[R2:[0-9]+]], r[[R1]], #32
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; NO-REALIGN: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128]
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; NO-REALIGN: add r[[R2:[0-9]+]], r[[R1]], #16
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; NO-REALIGN: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128]
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; NO-REALIGN: vst1.32 {{{d[0-9]+, d[0-9]+}}}, [r[[R1]]:128]!
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; NO-REALIGN: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R1]]:128]
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; NO-REALIGN: add r[[R2:[0-9]+]], r[[R0:0]], #48
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; NO-REALIGN: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128]
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; NO-REALIGN: add r[[R2:[0-9]+]], r[[R0]], #32
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; NO-REALIGN: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128]
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; NO-REALIGN: add r[[R2:[0-9]+]], r[[R1]], #16
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; NO-REALIGN: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128]
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; NO-REALIGN: vst1.32 {{{d[0-9]+, d[0-9]+}}}, [r[[R0]]:128]!
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; NO-REALIGN: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R0]]:128]
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%retval = alloca <16 x float>, align 16
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%0 = load <16 x float>* @T3_retval, align 16
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@ -44,8 +42,8 @@ define void @test2(<16 x float>* noalias sret %agg.result) nounwind ssp {
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entry:
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; REALIGN-LABEL: test2
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; REALIGN: bic sp, sp, #63
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; REALIGN: vld1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R1:[0-9]+]]:128]
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; REALIGN: add r[[R2:[0-9]+]], r[[R1]], #16
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; REALIGN: mov r[[R2:[0-9]+]], r[[R1:[0-9]+]]
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; REALIGN: vld1.32 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128]!
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; REALIGN: vld1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128]
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; REALIGN: add r[[R2:[0-9]+]], r[[R1]], #32
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; REALIGN: vld1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128]
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@ -65,8 +63,7 @@ entry:
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; REALIGN: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R1]]:128]
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; REALIGN: add r[[R1:[0-9]+]], r[[R0]], #32
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; REALIGN: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R1]]:128]
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; REALIGN: add r[[R1:[0-9]+]], r[[R0]], #16
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; REALIGN: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R1]]:128]
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; REALIGN: vst1.32 {{{d[0-9]+, d[0-9]+}}}, [r[[R0]]:128]!
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; REALIGN: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R0]]:128]
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%retval = alloca <16 x float>, align 16
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%0 = load <16 x float>* @T3_retval, align 16
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@ -46,10 +46,8 @@ entry:
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; CHECK: movw [[REG2:r[0-9]+]], #16716
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; CHECK: movt [[REG2:r[0-9]+]], #72
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; CHECK: str [[REG2]], [r0, #32]
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; CHECK: vld1.8 {d{{[0-9]+}}, d{{[0-9]+}}}, [r1]
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; CHECK: vst1.8 {d{{[0-9]+}}, d{{[0-9]+}}}, [r0]
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; CHECK: adds r0, #16
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; CHECK: adds r1, #16
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; CHECK: vld1.64 {d{{[0-9]+}}, d{{[0-9]+}}}, [r1]!
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; CHECK: vst1.64 {d{{[0-9]+}}, d{{[0-9]+}}}, [r0]!
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; CHECK: vld1.8 {d{{[0-9]+}}, d{{[0-9]+}}}, [r1]
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; CHECK: vst1.8 {d{{[0-9]+}}, d{{[0-9]+}}}, [r0]
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tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %C, i8* getelementptr inbounds ([36 x i8]* @.str2, i64 0, i64 0), i64 36, i32 1, i1 false)
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@ -59,10 +57,8 @@ entry:
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define void @t3(i8* nocapture %C) nounwind {
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entry:
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; CHECK-LABEL: t3:
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; CHECK: vld1.8 {d{{[0-9]+}}, d{{[0-9]+}}}, [r1]
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; CHECK: vst1.8 {d{{[0-9]+}}, d{{[0-9]+}}}, [r0]
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; CHECK: adds r0, #16
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; CHECK: adds r1, #16
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; CHECK: vld1.64 {d{{[0-9]+}}, d{{[0-9]+}}}, [r1]!
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; CHECK: vst1.64 {d{{[0-9]+}}, d{{[0-9]+}}}, [r0]!
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; CHECK: vld1.8 {d{{[0-9]+}}}, [r1]
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; CHECK: vst1.8 {d{{[0-9]+}}}, [r0]
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tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %C, i8* getelementptr inbounds ([24 x i8]* @.str3, i64 0, i64 0), i64 24, i32 1, i1 false)
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@ -73,7 +69,8 @@ define void @t4(i8* nocapture %C) nounwind {
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entry:
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; CHECK-LABEL: t4:
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; CHECK: vld1.8 {[[REG3:d[0-9]+]], [[REG4:d[0-9]+]]}, [r1]
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; CHECK: vst1.8 {[[REG3]], [[REG4]]}, [r0]
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; CHECK: vst1.64 {[[REG3]], [[REG4]]}, [r0]!
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; CHECK: strh [[REG5:r[0-9]+]], [r0]
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tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %C, i8* getelementptr inbounds ([18 x i8]* @.str4, i64 0, i64 0), i64 18, i32 1, i1 false)
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ret void
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}
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184
test/CodeGen/ARM/vector-load.ll
Normal file
184
test/CodeGen/ARM/vector-load.ll
Normal file
@ -0,0 +1,184 @@
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; RUN: llc < %s | FileCheck %s
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target datalayout = "e-m:o-p:32:32-i1:8:32-i8:8:32-i16:16:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"
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target triple = "thumbv7s-apple-ios8.0.0"
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define <8 x i8> @load_v8i8(<8 x i8>** %ptr) {
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;CHECK-LABEL: load_v8i8:
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;CHECK: vld1.8 {{{d[0-9]+}}}, [{{r[0-9]+}}]
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%A = load <8 x i8>** %ptr
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%lA = load <8 x i8>* %A, align 1
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ret <8 x i8> %lA
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}
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define <8 x i8> @load_v8i8_update(<8 x i8>** %ptr) {
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;CHECK-LABEL: load_v8i8_update:
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;CHECK: vld1.8 {{{d[0-9]+}}}, [{{r[0-9]+}}]!
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%A = load <8 x i8>** %ptr
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%lA = load <8 x i8>* %A, align 1
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%inc = getelementptr <8 x i8>* %A, i38 1
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store <8 x i8>* %inc, <8 x i8>** %ptr
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ret <8 x i8> %lA
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}
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define <4 x i16> @load_v4i16(<4 x i16>** %ptr) {
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;CHECK-LABEL: load_v4i16:
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;CHECK: vld1.8 {{{d[0-9]+}}}, [{{r[0-9]+}}]
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%A = load <4 x i16>** %ptr
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%lA = load <4 x i16>* %A, align 1
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ret <4 x i16> %lA
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}
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define <4 x i16> @load_v4i16_update(<4 x i16>** %ptr) {
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;CHECK-LABEL: load_v4i16_update:
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;CHECK: vld1.16 {{{d[0-9]+}}}, [{{r[0-9]+}}]!
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%A = load <4 x i16>** %ptr
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%lA = load <4 x i16>* %A, align 1
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%inc = getelementptr <4 x i16>* %A, i34 1
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store <4 x i16>* %inc, <4 x i16>** %ptr
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ret <4 x i16> %lA
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}
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define <2 x i32> @load_v2i32(<2 x i32>** %ptr) {
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;CHECK-LABEL: load_v2i32:
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;CHECK: vld1.8 {{{d[0-9]+}}}, [{{r[0-9]+}}]
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%A = load <2 x i32>** %ptr
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%lA = load <2 x i32>* %A, align 1
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ret <2 x i32> %lA
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}
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define <2 x i32> @load_v2i32_update(<2 x i32>** %ptr) {
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;CHECK-LABEL: load_v2i32_update:
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;CHECK: vld1.32 {{{d[0-9]+}}}, [{{r[0-9]+}}]!
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%A = load <2 x i32>** %ptr
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%lA = load <2 x i32>* %A, align 1
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%inc = getelementptr <2 x i32>* %A, i32 1
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store <2 x i32>* %inc, <2 x i32>** %ptr
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ret <2 x i32> %lA
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}
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define <2 x float> @load_v2f32(<2 x float>** %ptr) {
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;CHECK-LABEL: load_v2f32:
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;CHECK: vld1.8 {{{d[0-9]+}}}, [{{r[0-9]+}}]
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%A = load <2 x float>** %ptr
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%lA = load <2 x float>* %A, align 1
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ret <2 x float> %lA
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}
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define <2 x float> @load_v2f32_update(<2 x float>** %ptr) {
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;CHECK-LABEL: load_v2f32_update:
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;CHECK: vld1.32 {{{d[0-9]+}}}, [{{r[0-9]+}}]!
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%A = load <2 x float>** %ptr
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%lA = load <2 x float>* %A, align 1
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%inc = getelementptr <2 x float>* %A, i32 1
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store <2 x float>* %inc, <2 x float>** %ptr
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ret <2 x float> %lA
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}
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define <1 x i64> @load_v1i64(<1 x i64>** %ptr) {
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;CHECK-LABEL: load_v1i64:
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;CHECK: vld1.8 {{{d[0-9]+}}}, [{{r[0-9]+}}]
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%A = load <1 x i64>** %ptr
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%lA = load <1 x i64>* %A, align 1
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ret <1 x i64> %lA
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}
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define <1 x i64> @load_v1i64_update(<1 x i64>** %ptr) {
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;CHECK-LABEL: load_v1i64_update:
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;CHECK: vld1.64 {{{d[0-9]+}}}, [{{r[0-9]+}}]!
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%A = load <1 x i64>** %ptr
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%lA = load <1 x i64>* %A, align 1
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%inc = getelementptr <1 x i64>* %A, i31 1
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store <1 x i64>* %inc, <1 x i64>** %ptr
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ret <1 x i64> %lA
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}
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define <16 x i8> @load_v16i8(<16 x i8>** %ptr) {
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;CHECK-LABEL: load_v16i8:
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;CHECK: vld1.8 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]
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%A = load <16 x i8>** %ptr
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%lA = load <16 x i8>* %A, align 1
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ret <16 x i8> %lA
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}
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||||
define <16 x i8> @load_v16i8_update(<16 x i8>** %ptr) {
|
||||
;CHECK-LABEL: load_v16i8_update:
|
||||
;CHECK: vld1.8 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]!
|
||||
%A = load <16 x i8>** %ptr
|
||||
%lA = load <16 x i8>* %A, align 1
|
||||
%inc = getelementptr <16 x i8>* %A, i316 1
|
||||
store <16 x i8>* %inc, <16 x i8>** %ptr
|
||||
ret <16 x i8> %lA
|
||||
}
|
||||
|
||||
define <8 x i16> @load_v8i16(<8 x i16>** %ptr) {
|
||||
;CHECK-LABEL: load_v8i16:
|
||||
;CHECK: vld1.8 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]
|
||||
%A = load <8 x i16>** %ptr
|
||||
%lA = load <8 x i16>* %A, align 1
|
||||
ret <8 x i16> %lA
|
||||
}
|
||||
|
||||
define <8 x i16> @load_v8i16_update(<8 x i16>** %ptr) {
|
||||
;CHECK-LABEL: load_v8i16_update:
|
||||
;CHECK: vld1.16 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]!
|
||||
%A = load <8 x i16>** %ptr
|
||||
%lA = load <8 x i16>* %A, align 1
|
||||
%inc = getelementptr <8 x i16>* %A, i38 1
|
||||
store <8 x i16>* %inc, <8 x i16>** %ptr
|
||||
ret <8 x i16> %lA
|
||||
}
|
||||
|
||||
define <4 x i32> @load_v4i32(<4 x i32>** %ptr) {
|
||||
;CHECK-LABEL: load_v4i32:
|
||||
;CHECK: vld1.8 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]
|
||||
%A = load <4 x i32>** %ptr
|
||||
%lA = load <4 x i32>* %A, align 1
|
||||
ret <4 x i32> %lA
|
||||
}
|
||||
|
||||
define <4 x i32> @load_v4i32_update(<4 x i32>** %ptr) {
|
||||
;CHECK-LABEL: load_v4i32_update:
|
||||
;CHECK: vld1.32 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]!
|
||||
%A = load <4 x i32>** %ptr
|
||||
%lA = load <4 x i32>* %A, align 1
|
||||
%inc = getelementptr <4 x i32>* %A, i34 1
|
||||
store <4 x i32>* %inc, <4 x i32>** %ptr
|
||||
ret <4 x i32> %lA
|
||||
}
|
||||
|
||||
define <4 x float> @load_v4f32(<4 x float>** %ptr) {
|
||||
;CHECK-LABEL: load_v4f32:
|
||||
;CHECK: vld1.8 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]
|
||||
%A = load <4 x float>** %ptr
|
||||
%lA = load <4 x float>* %A, align 1
|
||||
ret <4 x float> %lA
|
||||
}
|
||||
|
||||
define <4 x float> @load_v4f32_update(<4 x float>** %ptr) {
|
||||
;CHECK-LABEL: load_v4f32_update:
|
||||
;CHECK: vld1.32 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]!
|
||||
%A = load <4 x float>** %ptr
|
||||
%lA = load <4 x float>* %A, align 1
|
||||
%inc = getelementptr <4 x float>* %A, i34 1
|
||||
store <4 x float>* %inc, <4 x float>** %ptr
|
||||
ret <4 x float> %lA
|
||||
}
|
||||
|
||||
define <2 x i64> @load_v2i64(<2 x i64>** %ptr) {
|
||||
;CHECK-LABEL: load_v2i64:
|
||||
;CHECK: vld1.8 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]
|
||||
%A = load <2 x i64>** %ptr
|
||||
%lA = load <2 x i64>* %A, align 1
|
||||
ret <2 x i64> %lA
|
||||
}
|
||||
|
||||
define <2 x i64> @load_v2i64_update(<2 x i64>** %ptr) {
|
||||
;CHECK-LABEL: load_v2i64_update:
|
||||
;CHECK: vld1.64 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]!
|
||||
%A = load <2 x i64>** %ptr
|
||||
%lA = load <2 x i64>* %A, align 1
|
||||
%inc = getelementptr <2 x i64>* %A, i32 1
|
||||
store <2 x i64>* %inc, <2 x i64>** %ptr
|
||||
ret <2 x i64> %lA
|
||||
}
|
||||
184
test/CodeGen/ARM/vector-store.ll
Normal file
184
test/CodeGen/ARM/vector-store.ll
Normal file
@ -0,0 +1,184 @@
|
||||
; RUN: llc < %s | FileCheck %s
|
||||
|
||||
target datalayout = "e-m:o-p:32:32-i1:8:32-i8:8:32-i16:16:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"
|
||||
target triple = "thumbv7s-apple-ios8.0.0"
|
||||
|
||||
define void @store_v8i8(<8 x i8>** %ptr, <8 x i8> %val) {
|
||||
;CHECK-LABEL: store_v8i8:
|
||||
;CHECK: str r1, [r0]
|
||||
%A = load <8 x i8>** %ptr
|
||||
store <8 x i8> %val, <8 x i8>* %A, align 1
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @store_v8i8_update(<8 x i8>** %ptr, <8 x i8> %val) {
|
||||
;CHECK-LABEL: store_v8i8_update:
|
||||
;CHECK: vst1.8 {{{d[0-9]+}}}, [{{r[0-9]+}}]!
|
||||
%A = load <8 x i8>** %ptr
|
||||
store <8 x i8> %val, <8 x i8>* %A, align 1
|
||||
%inc = getelementptr <8 x i8>* %A, i38 1
|
||||
store <8 x i8>* %inc, <8 x i8>** %ptr
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @store_v4i16(<4 x i16>** %ptr, <4 x i16> %val) {
|
||||
;CHECK-LABEL: store_v4i16:
|
||||
;CHECK: str r1, [r0]
|
||||
%A = load <4 x i16>** %ptr
|
||||
store <4 x i16> %val, <4 x i16>* %A, align 1
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @store_v4i16_update(<4 x i16>** %ptr, <4 x i16> %val) {
|
||||
;CHECK-LABEL: store_v4i16_update:
|
||||
;CHECK: vst1.16 {{{d[0-9]+}}}, [{{r[0-9]+}}]!
|
||||
%A = load <4 x i16>** %ptr
|
||||
store <4 x i16> %val, <4 x i16>* %A, align 1
|
||||
%inc = getelementptr <4 x i16>* %A, i34 1
|
||||
store <4 x i16>* %inc, <4 x i16>** %ptr
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @store_v2i32(<2 x i32>** %ptr, <2 x i32> %val) {
|
||||
;CHECK-LABEL: store_v2i32:
|
||||
;CHECK: str r1, [r0]
|
||||
%A = load <2 x i32>** %ptr
|
||||
store <2 x i32> %val, <2 x i32>* %A, align 1
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @store_v2i32_update(<2 x i32>** %ptr, <2 x i32> %val) {
|
||||
;CHECK-LABEL: store_v2i32_update:
|
||||
;CHECK: vst1.32 {{{d[0-9]+}}}, [{{r[0-9]+}}]!
|
||||
%A = load <2 x i32>** %ptr
|
||||
store <2 x i32> %val, <2 x i32>* %A, align 1
|
||||
%inc = getelementptr <2 x i32>* %A, i32 1
|
||||
store <2 x i32>* %inc, <2 x i32>** %ptr
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @store_v2f32(<2 x float>** %ptr, <2 x float> %val) {
|
||||
;CHECK-LABEL: store_v2f32:
|
||||
;CHECK: str r1, [r0]
|
||||
%A = load <2 x float>** %ptr
|
||||
store <2 x float> %val, <2 x float>* %A, align 1
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @store_v2f32_update(<2 x float>** %ptr, <2 x float> %val) {
|
||||
;CHECK-LABEL: store_v2f32_update:
|
||||
;CHECK: vst1.32 {{{d[0-9]+}}}, [{{r[0-9]+}}]!
|
||||
%A = load <2 x float>** %ptr
|
||||
store <2 x float> %val, <2 x float>* %A, align 1
|
||||
%inc = getelementptr <2 x float>* %A, i32 1
|
||||
store <2 x float>* %inc, <2 x float>** %ptr
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @store_v1i64(<1 x i64>** %ptr, <1 x i64> %val) {
|
||||
;CHECK-LABEL: store_v1i64:
|
||||
;CHECK: str r1, [r0]
|
||||
%A = load <1 x i64>** %ptr
|
||||
store <1 x i64> %val, <1 x i64>* %A, align 1
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @store_v1i64_update(<1 x i64>** %ptr, <1 x i64> %val) {
|
||||
;CHECK-LABEL: store_v1i64_update:
|
||||
;CHECK: vst1.64 {{{d[0-9]+}}}, [{{r[0-9]+}}]!
|
||||
%A = load <1 x i64>** %ptr
|
||||
store <1 x i64> %val, <1 x i64>* %A, align 1
|
||||
%inc = getelementptr <1 x i64>* %A, i31 1
|
||||
store <1 x i64>* %inc, <1 x i64>** %ptr
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @store_v16i8(<16 x i8>** %ptr, <16 x i8> %val) {
|
||||
;CHECK-LABEL: store_v16i8:
|
||||
;CHECK: vst1.8 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]
|
||||
%A = load <16 x i8>** %ptr
|
||||
store <16 x i8> %val, <16 x i8>* %A, align 1
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @store_v16i8_update(<16 x i8>** %ptr, <16 x i8> %val) {
|
||||
;CHECK-LABEL: store_v16i8_update:
|
||||
;CHECK: vst1.8 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]!
|
||||
%A = load <16 x i8>** %ptr
|
||||
store <16 x i8> %val, <16 x i8>* %A, align 1
|
||||
%inc = getelementptr <16 x i8>* %A, i316 1
|
||||
store <16 x i8>* %inc, <16 x i8>** %ptr
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @store_v8i16(<8 x i16>** %ptr, <8 x i16> %val) {
|
||||
;CHECK-LABEL: store_v8i16:
|
||||
;CHECK: vst1.8 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]
|
||||
%A = load <8 x i16>** %ptr
|
||||
store <8 x i16> %val, <8 x i16>* %A, align 1
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @store_v8i16_update(<8 x i16>** %ptr, <8 x i16> %val) {
|
||||
;CHECK-LABEL: store_v8i16_update:
|
||||
;CHECK: vst1.16 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]!
|
||||
%A = load <8 x i16>** %ptr
|
||||
store <8 x i16> %val, <8 x i16>* %A, align 1
|
||||
%inc = getelementptr <8 x i16>* %A, i38 1
|
||||
store <8 x i16>* %inc, <8 x i16>** %ptr
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @store_v4i32(<4 x i32>** %ptr, <4 x i32> %val) {
|
||||
;CHECK-LABEL: store_v4i32:
|
||||
;CHECK: vst1.8 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]
|
||||
%A = load <4 x i32>** %ptr
|
||||
store <4 x i32> %val, <4 x i32>* %A, align 1
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @store_v4i32_update(<4 x i32>** %ptr, <4 x i32> %val) {
|
||||
;CHECK-LABEL: store_v4i32_update:
|
||||
;CHECK: vst1.32 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]!
|
||||
%A = load <4 x i32>** %ptr
|
||||
store <4 x i32> %val, <4 x i32>* %A, align 1
|
||||
%inc = getelementptr <4 x i32>* %A, i34 1
|
||||
store <4 x i32>* %inc, <4 x i32>** %ptr
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @store_v4f32(<4 x float>** %ptr, <4 x float> %val) {
|
||||
;CHECK-LABEL: store_v4f32:
|
||||
;CHECK: vst1.8 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]
|
||||
%A = load <4 x float>** %ptr
|
||||
store <4 x float> %val, <4 x float>* %A, align 1
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @store_v4f32_update(<4 x float>** %ptr, <4 x float> %val) {
|
||||
;CHECK-LABEL: store_v4f32_update:
|
||||
;CHECK: vst1.32 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]!
|
||||
%A = load <4 x float>** %ptr
|
||||
store <4 x float> %val, <4 x float>* %A, align 1
|
||||
%inc = getelementptr <4 x float>* %A, i34 1
|
||||
store <4 x float>* %inc, <4 x float>** %ptr
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @store_v2i64(<2 x i64>** %ptr, <2 x i64> %val) {
|
||||
;CHECK-LABEL: store_v2i64:
|
||||
;CHECK: vst1.8 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]
|
||||
%A = load <2 x i64>** %ptr
|
||||
store <2 x i64> %val, <2 x i64>* %A, align 1
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @store_v2i64_update(<2 x i64>** %ptr, <2 x i64> %val) {
|
||||
;CHECK-LABEL: store_v2i64_update:
|
||||
;CHECK: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]!
|
||||
%A = load <2 x i64>** %ptr
|
||||
store <2 x i64> %val, <2 x i64>* %A, align 1
|
||||
%inc = getelementptr <2 x i64>* %A, i32 1
|
||||
store <2 x i64>* %inc, <2 x i64>** %ptr
|
||||
ret void
|
||||
}
|
||||
@ -201,7 +201,7 @@ for.end: ; preds = %for.body
|
||||
;
|
||||
; Currently we have three extra add.w's that keep the store address
|
||||
; live past the next increment because ISEL is unfortunately undoing
|
||||
; the store chain. ISEL also fails to convert the stores to
|
||||
; the store chain. ISEL also fails to convert all but one of the stores to
|
||||
; post-increment addressing. However, the loads should use
|
||||
; post-increment addressing, no add's or add.w's beyond the three
|
||||
; mentioned. Most importantly, there should be no spills or reloads!
|
||||
@ -210,7 +210,7 @@ for.end: ; preds = %for.body
|
||||
; A9: %.lr.ph
|
||||
; A9-NOT: lsl.w
|
||||
; A9-NOT: {{ldr|str|adds|add r}}
|
||||
; A9: add.w r
|
||||
; A9: vst1.8 {{.*}} [r{{[0-9]+}}]!
|
||||
; A9-NOT: {{ldr|str|adds|add r}}
|
||||
; A9: add.w r
|
||||
; A9-NOT: {{ldr|str|adds|add r}}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user