mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2025-01-27 14:34:58 +00:00
[DAGCombiner] teach how to simplify xor/and/or nodes according to the following rules:
1) (AND (shuf (A, C, Mask), shuf (B, C, Mask)) -> shuf (AND (A, B), C, Mask) 2) (OR (shuf (A, C, Mask), shuf (B, C, Mask)) -> shuf (OR (A, B), C, Mask) 3) (XOR (shuf (A, C, Mask), shuf (B, C, Mask)) -> shuf (XOR (A, B), V_0, Mask) 4) (AND (shuf (C, A, Mask), shuf (C, B, Mask)) -> shuf (C, AND (A, B), Mask) 5) (OR (shuf (C, A, Mask), shuf (C, B, Mask)) -> shuf (C, OR (A, B), Mask) 6) (XOR (shuf (C, A, Mask), shuf (C, B, Mask)) -> shuf (V_0, XOR (A, B), Mask) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204160 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Andrea Di Biagio
parent
7e18b99f1e
commit
6077ca9abb
@ -2518,35 +2518,66 @@ SDValue DAGCombiner::SimplifyBinOpWithSameOpcodeHands(SDNode *N) {
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// The type-legalizer generates this pattern when loading illegal
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// vector types from memory. In many cases this allows additional shuffle
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// optimizations.
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if (N0.getOpcode() == ISD::VECTOR_SHUFFLE && Level < AfterLegalizeDAG &&
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N0.getOperand(1).getOpcode() == ISD::UNDEF &&
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N1.getOperand(1).getOpcode() == ISD::UNDEF) {
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// There are other cases where moving the shuffle after the xor/and/or
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// is profitable even if shuffles don't perform a swizzle.
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// If both shuffles use the same mask, and both shuffles have the same first
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// or second operand, then it might still be profitable to move the shuffle
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// after the xor/and/or operation.
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if (N0.getOpcode() == ISD::VECTOR_SHUFFLE && Level < AfterLegalizeDAG) {
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ShuffleVectorSDNode *SVN0 = cast<ShuffleVectorSDNode>(N0);
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ShuffleVectorSDNode *SVN1 = cast<ShuffleVectorSDNode>(N1);
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assert(N0.getOperand(0).getValueType() == N1.getOperand(1).getValueType() &&
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assert(N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType() &&
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"Inputs to shuffles are not the same type");
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unsigned NumElts = VT.getVectorNumElements();
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// Check that both shuffles use the same mask. The masks are known to be of
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// the same length because the result vector type is the same.
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bool SameMask = true;
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for (unsigned i = 0; i != NumElts; ++i) {
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int Idx0 = SVN0->getMaskElt(i);
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int Idx1 = SVN1->getMaskElt(i);
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if (Idx0 != Idx1) {
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SameMask = false;
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break;
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}
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}
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// Check also that shuffles have only one use to avoid introducing extra
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// instructions.
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if (SVN0->hasOneUse() && SVN1->hasOneUse() &&
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SVN0->getMask().equals(SVN1->getMask())) {
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SDValue ShOp = N0->getOperand(1);
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if (SameMask) {
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SDValue Op = DAG.getNode(N->getOpcode(), SDLoc(N), VT,
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N0.getOperand(0), N1.getOperand(0));
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AddToWorkList(Op.getNode());
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return DAG.getVectorShuffle(VT, SDLoc(N), Op,
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DAG.getUNDEF(VT), &SVN0->getMask()[0]);
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// Don't try to fold this node if it requires introducing a
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// build vector of all zeros that might be illegal at this stage.
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if (N->getOpcode() == ISD::XOR && ShOp.getOpcode() != ISD::UNDEF) {
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if (!LegalTypes)
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ShOp = DAG.getConstant(0, VT);
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else
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ShOp = SDValue();
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}
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// (AND (shuf (A, C), shuf (B, C)) -> shuf (AND (A, B), C)
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// (OR (shuf (A, C), shuf (B, C)) -> shuf (OR (A, B), C)
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// (XOR (shuf (A, C), shuf (B, C)) -> shuf (XOR (A, B), V_0)
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if (N0.getOperand(1) == N1.getOperand(1) && ShOp.getNode()) {
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SDValue NewNode = DAG.getNode(N->getOpcode(), SDLoc(N), VT,
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N0->getOperand(0), N1->getOperand(0));
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AddToWorkList(NewNode.getNode());
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return DAG.getVectorShuffle(VT, SDLoc(N), NewNode, ShOp,
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&SVN0->getMask()[0]);
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}
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// Don't try to fold this node if it requires introducing a
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// build vector of all zeros that might be illegal at this stage.
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ShOp = N0->getOperand(0);
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if (N->getOpcode() == ISD::XOR && ShOp.getOpcode() != ISD::UNDEF) {
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if (!LegalTypes)
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ShOp = DAG.getConstant(0, VT);
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else
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ShOp = SDValue();
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}
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// (AND (shuf (C, A), shuf (C, B)) -> shuf (C, AND (A, B))
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// (OR (shuf (C, A), shuf (C, B)) -> shuf (C, OR (A, B))
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// (XOR (shuf (C, A), shuf (C, B)) -> shuf (V_0, XOR (A, B))
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if (N0->getOperand(0) == N1->getOperand(0) && ShOp.getNode()) {
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SDValue NewNode = DAG.getNode(N->getOpcode(), SDLoc(N), VT,
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N0->getOperand(1), N1->getOperand(1));
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AddToWorkList(NewNode.getNode());
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return DAG.getVectorShuffle(VT, SDLoc(N), ShOp, NewNode,
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&SVN0->getMask()[0]);
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}
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}
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}
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@ -251,6 +251,7 @@ define <2 x i64> @test20(<2 x i64> %a, <2 x i64> %b) {
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; CHECK-LABEL: test20
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; CHECK-NOT: xorps
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; CHECK: orps
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; CHECK-NEXT: movq
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; CHECK-NEXT: ret
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@ -262,6 +263,7 @@ define <2 x i64> @test21(<2 x i64> %a, <2 x i64> %b) {
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}
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; CHECK-LABEL: test21
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; CHECK: por
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; CHECK-NEXT: pslldq
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; CHECK-NEXT: ret
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253
test/CodeGen/X86/combine-vec-shuffle.ll
Normal file
253
test/CodeGen/X86/combine-vec-shuffle.ll
Normal file
@ -0,0 +1,253 @@
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; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -mcpu=corei7 | FileCheck %s
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; Verify that the DAGCombiner correctly folds according to the following rules:
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; fold (AND (shuf (A, C), shuf (B, C)) -> shuf (AND (A, B), C)
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; fold (OR (shuf (A, C), shuf (B, C)) -> shuf (OR (A, B), C)
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; fold (XOR (shuf (A, C), shuf (B, C)) -> shuf (XOR (A, B), V_0)
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; fold (AND (shuf (C, A), shuf (C, B)) -> shuf (C, AND (A, B))
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; fold (OR (shuf (C, A), shuf (C, B)) -> shuf (C, OR (A, B))
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; fold (XOR (shuf (C, A), shuf (C, B)) -> shuf (V_0, XOR (A, B))
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define <4 x i32> @test1(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
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%shuf1 = shufflevector <4 x i32> %a, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 1, i32 3>
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%shuf2 = shufflevector <4 x i32> %b, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 1, i32 3>
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%and = and <4 x i32> %shuf1, %shuf2
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ret <4 x i32> %and
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}
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; CHECK-LABEL: test1
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; CHECK-NOT: pshufd
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; CHECK: pand
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; CHECK-NEXT: pshufd
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; CHECK-NEXT: ret
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define <4 x i32> @test2(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
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%shuf1 = shufflevector <4 x i32> %a, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 1, i32 3>
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%shuf2 = shufflevector <4 x i32> %b, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 1, i32 3>
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%or = or <4 x i32> %shuf1, %shuf2
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ret <4 x i32> %or
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}
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; CHECK-LABEL: test2
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; CHECK-NOT: pshufd
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; CHECK: por
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; CHECK-NEXT: pshufd
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; CHECK-NEXT: ret
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define <4 x i32> @test3(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
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%shuf1 = shufflevector <4 x i32> %a, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 1, i32 3>
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%shuf2 = shufflevector <4 x i32> %b, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 1, i32 3>
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%xor = xor <4 x i32> %shuf1, %shuf2
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ret <4 x i32> %xor
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}
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; CHECK-LABEL: test3
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; CHECK-NOT: pshufd
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; CHECK: pxor
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; CHECK-NEXT: pshufd
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; CHECK-NEXT: ret
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define <4 x i32> @test4(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
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%shuf1 = shufflevector <4 x i32> %c, <4 x i32> %a, <4 x i32><i32 4, i32 6, i32 5, i32 7>
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%shuf2 = shufflevector <4 x i32> %c, <4 x i32> %b, <4 x i32><i32 4, i32 6, i32 5, i32 7>
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%and = and <4 x i32> %shuf1, %shuf2
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ret <4 x i32> %and
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}
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; CHECK-LABEL: test4
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; CHECK-NOT: pshufd
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; CHECK: pand
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; CHECK-NEXT: pshufd
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; CHECK-NEXT: ret
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define <4 x i32> @test5(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
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%shuf1 = shufflevector <4 x i32> %c, <4 x i32> %a, <4 x i32><i32 4, i32 6, i32 5, i32 7>
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%shuf2 = shufflevector <4 x i32> %c, <4 x i32> %b, <4 x i32><i32 4, i32 6, i32 5, i32 7>
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%or = or <4 x i32> %shuf1, %shuf2
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ret <4 x i32> %or
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}
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; CHECK-LABEL: test5
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; CHECK-NOT: pshufd
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; CHECK: por
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; CHECK-NEXT: pshufd
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; CHECK-NEXT: ret
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define <4 x i32> @test6(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
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%shuf1 = shufflevector <4 x i32> %c, <4 x i32> %a, <4 x i32><i32 4, i32 6, i32 5, i32 7>
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%shuf2 = shufflevector <4 x i32> %c, <4 x i32> %b, <4 x i32><i32 4, i32 6, i32 5, i32 7>
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%xor = xor <4 x i32> %shuf1, %shuf2
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ret <4 x i32> %xor
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}
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; CHECK-LABEL: test6
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; CHECK-NOT: pshufd
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; CHECK: pxor
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; CHECK-NEXT: pshufd
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; CHECK-NEXT: ret
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; Verify that DAGCombiner moves the shuffle after the xor/and/or even if shuffles
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; are not performing a swizzle operations.
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define <4 x i32> @test1b(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
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%shuf1 = shufflevector <4 x i32> %a, <4 x i32> %c, <4 x i32><i32 0, i32 5, i32 2, i32 7>
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%shuf2 = shufflevector <4 x i32> %b, <4 x i32> %c, <4 x i32><i32 0, i32 5, i32 2, i32 7>
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%and = and <4 x i32> %shuf1, %shuf2
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ret <4 x i32> %and
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}
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; CHECK-LABEL: test1b
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; CHECK-NOT: blendps
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; CHECK: andps
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; CHECK-NEXT: blendps
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; CHECK-NEXT: ret
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define <4 x i32> @test2b(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
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%shuf1 = shufflevector <4 x i32> %a, <4 x i32> %c, <4 x i32><i32 0, i32 5, i32 2, i32 7>
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%shuf2 = shufflevector <4 x i32> %b, <4 x i32> %c, <4 x i32><i32 0, i32 5, i32 2, i32 7>
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%or = or <4 x i32> %shuf1, %shuf2
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ret <4 x i32> %or
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}
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; CHECK-LABEL: test2b
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; CHECK-NOT: blendps
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; CHECK: orps
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; CHECK-NEXT: blendps
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; CHECK-NEXT: ret
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define <4 x i32> @test3b(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
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%shuf1 = shufflevector <4 x i32> %a, <4 x i32> %c, <4 x i32><i32 0, i32 5, i32 2, i32 7>
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%shuf2 = shufflevector <4 x i32> %b, <4 x i32> %c, <4 x i32><i32 0, i32 5, i32 2, i32 7>
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%xor = xor <4 x i32> %shuf1, %shuf2
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ret <4 x i32> %xor
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}
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; CHECK-LABEL: test3b
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; CHECK-NOT: blendps
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; CHECK: xorps
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; CHECK-NEXT: xorps
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; CHECK-NEXT: blendps
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; CHECK-NEXT: ret
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define <4 x i32> @test4b(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
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%shuf1 = shufflevector <4 x i32> %c, <4 x i32> %a, <4 x i32><i32 0, i32 5, i32 2, i32 7>
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%shuf2 = shufflevector <4 x i32> %c, <4 x i32> %b, <4 x i32><i32 0, i32 5, i32 2, i32 7>
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%and = and <4 x i32> %shuf1, %shuf2
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ret <4 x i32> %and
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}
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; CHECK-LABEL: test4b
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; CHECK-NOT: blendps
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; CHECK: andps
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; CHECK-NEXT: blendps
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; CHECK: ret
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define <4 x i32> @test5b(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
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%shuf1 = shufflevector <4 x i32> %c, <4 x i32> %a, <4 x i32><i32 0, i32 5, i32 2, i32 7>
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%shuf2 = shufflevector <4 x i32> %c, <4 x i32> %b, <4 x i32><i32 0, i32 5, i32 2, i32 7>
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%or = or <4 x i32> %shuf1, %shuf2
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ret <4 x i32> %or
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}
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; CHECK-LABEL: test5b
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; CHECK-NOT: blendps
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; CHECK: orps
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; CHECK-NEXT: blendps
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; CHECK: ret
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define <4 x i32> @test6b(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
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%shuf1 = shufflevector <4 x i32> %c, <4 x i32> %a, <4 x i32><i32 0, i32 5, i32 2, i32 7>
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%shuf2 = shufflevector <4 x i32> %c, <4 x i32> %b, <4 x i32><i32 0, i32 5, i32 2, i32 7>
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%xor = xor <4 x i32> %shuf1, %shuf2
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ret <4 x i32> %xor
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}
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; CHECK-LABEL: test6b
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; CHECK-NOT: blendps
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; CHECK: xorps
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; CHECK-NEXT: xorps
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; CHECK-NEXT: blendps
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; CHECK: ret
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define <4 x i32> @test1c(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
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%shuf1 = shufflevector <4 x i32> %a, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 5, i32 7>
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%shuf2 = shufflevector <4 x i32> %b, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 5, i32 7>
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%and = and <4 x i32> %shuf1, %shuf2
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ret <4 x i32> %and
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}
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; CHECK-LABEL: test1c
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; CHECK-NOT: shufps
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; CHECK: andps
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; CHECK-NEXT: shufps
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; CHECK-NEXT: ret
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define <4 x i32> @test2c(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
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%shuf1 = shufflevector <4 x i32> %a, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 5, i32 7>
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%shuf2 = shufflevector <4 x i32> %b, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 5, i32 7>
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%or = or <4 x i32> %shuf1, %shuf2
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ret <4 x i32> %or
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}
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; CHECK-LABEL: test2c
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; CHECK-NOT: shufps
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; CHECK: orps
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; CHECK-NEXT: shufps
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; CHECK-NEXT: ret
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define <4 x i32> @test3c(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
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%shuf1 = shufflevector <4 x i32> %a, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 5, i32 7>
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%shuf2 = shufflevector <4 x i32> %b, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 5, i32 7>
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%xor = xor <4 x i32> %shuf1, %shuf2
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ret <4 x i32> %xor
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}
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; CHECK-LABEL: test3c
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; CHECK-NOT: shufps
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; CHECK: xorps
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; CHECK-NEXT: xorps
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; CHECK-NEXT: shufps
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; CHECK-NEXT: ret
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define <4 x i32> @test4c(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
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%shuf1 = shufflevector <4 x i32> %c, <4 x i32> %a, <4 x i32><i32 0, i32 2, i32 5, i32 7>
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%shuf2 = shufflevector <4 x i32> %c, <4 x i32> %b, <4 x i32><i32 0, i32 2, i32 5, i32 7>
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%and = and <4 x i32> %shuf1, %shuf2
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ret <4 x i32> %and
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}
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; CHECK-LABEL: test4c
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; CHECK-NOT: shufps
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; CHECK: andps
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; CHECK-NEXT: shufps
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; CHECK: ret
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||||
|
||||
define <4 x i32> @test5c(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
|
||||
%shuf1 = shufflevector <4 x i32> %c, <4 x i32> %a, <4 x i32><i32 0, i32 2, i32 5, i32 7>
|
||||
%shuf2 = shufflevector <4 x i32> %c, <4 x i32> %b, <4 x i32><i32 0, i32 2, i32 5, i32 7>
|
||||
%or = or <4 x i32> %shuf1, %shuf2
|
||||
ret <4 x i32> %or
|
||||
}
|
||||
; CHECK-LABEL: test5c
|
||||
; CHECK-NOT: shufps
|
||||
; CHECK: orps
|
||||
; CHECK-NEXT: shufps
|
||||
; CHECK: ret
|
||||
|
||||
|
||||
define <4 x i32> @test6c(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
|
||||
%shuf1 = shufflevector <4 x i32> %c, <4 x i32> %a, <4 x i32><i32 0, i32 2, i32 5, i32 7>
|
||||
%shuf2 = shufflevector <4 x i32> %c, <4 x i32> %b, <4 x i32><i32 0, i32 2, i32 5, i32 7>
|
||||
%xor = xor <4 x i32> %shuf1, %shuf2
|
||||
ret <4 x i32> %xor
|
||||
}
|
||||
; CHECK-LABEL: test6c
|
||||
; CHECK-NOT: shufps
|
||||
; CHECK: xorps
|
||||
; CHECK-NEXT: xorps
|
||||
; CHECK-NEXT: shufps
|
||||
; CHECK: ret
|
||||
|
||||
Loading…
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Reference in New Issue
Block a user