diff --git a/lib/CodeGen/LiveIntervalAnalysis.cpp b/lib/CodeGen/LiveIntervalAnalysis.cpp
index f48be4d5eb0..b71e819f0d3 100644
--- a/lib/CodeGen/LiveIntervalAnalysis.cpp
+++ b/lib/CodeGen/LiveIntervalAnalysis.cpp
@@ -192,8 +192,7 @@ void LiveIntervals::computeVirtRegInterval(LiveInterval &LI) {
   assert(LRCalc && "LRCalc not initialized.");
   assert(LI.empty() && "Should only compute empty intervals.");
   LRCalc->reset(MF, getSlotIndexes(), DomTree, &getVNInfoAllocator());
-  LRCalc->createDeadDefs(LI);
-  LRCalc->extendToUses(LI);
+  LRCalc->calculate(LI);
   computeDeadValues(LI, LI);
 }
 
@@ -251,22 +250,15 @@ void LiveIntervals::computeRegUnitRange(LiveRange &LR, unsigned Unit) {
   // may share super-registers. That's OK because createDeadDefs() is
   // idempotent. It is very rare for a register unit to have multiple roots, so
   // uniquing super-registers is probably not worthwhile.
-  for (MCRegUnitRootIterator Roots(Unit, TRI); Roots.isValid(); ++Roots) {
-    for (MCSuperRegIterator Supers(*Roots, TRI, /*IncludeSelf=*/true);
-         Supers.isValid(); ++Supers) {
-      if (!MRI->reg_empty(*Supers))
-        LRCalc->createDeadDefs(LR, *Supers);
-    }
-  }
-
-  // Now extend LR to reach all uses.
-  // Ignore uses of reserved registers. We only track defs of those.
   for (MCRegUnitRootIterator Roots(Unit, TRI); Roots.isValid(); ++Roots) {
     for (MCSuperRegIterator Supers(*Roots, TRI, /*IncludeSelf=*/true);
          Supers.isValid(); ++Supers) {
       unsigned Reg = *Supers;
-      if (!MRI->isReserved(Reg) && !MRI->reg_empty(Reg))
-        LRCalc->extendToUses(LR, Reg);
+      if (MRI->reg_empty(Reg))
+        continue;
+      // Ignore uses of reserved registers. We only track defs of those.
+      bool IgnoreUses = MRI->isReserved(Reg);
+      LRCalc->calculate(LR, *Supers, IgnoreUses);
     }
   }
 }
diff --git a/lib/CodeGen/LiveRangeCalc.cpp b/lib/CodeGen/LiveRangeCalc.cpp
index 37ca87cd69d..040148f065e 100644
--- a/lib/CodeGen/LiveRangeCalc.cpp
+++ b/lib/CodeGen/LiveRangeCalc.cpp
@@ -29,31 +29,35 @@ void LiveRangeCalc::reset(const MachineFunction *mf,
   DomTree = MDT;
   Alloc = VNIA;
 
-  MainLiveOutData.reset(MF->getNumBlockIDs());
-  LiveIn.clear();
+  unsigned NumBlocks = MF->getNumBlockIDs();
+  Seen.clear();
+  Seen.resize(NumBlocks);
+  Map.resize(NumBlocks);
 }
 
 
-static SlotIndex getDefIndex(const SlotIndexes &Indexes, const MachineInstr &MI,
-                             bool EarlyClobber) {
-  // PHI defs begin at the basic block start index.
-  if (MI.isPHI())
-    return Indexes.getMBBStartIdx(MI.getParent());
-
-  // Instructions are either normal 'r', or early clobber 'e'.
-  return Indexes.getInstructionIndex(&MI).getRegSlot(EarlyClobber);
+static void createDeadDef(SlotIndexes &Indexes, VNInfo::Allocator &Alloc,
+                          LiveRange &LR, const MachineOperand &MO) {
+    const MachineInstr *MI = MO.getParent();
+    SlotIndex DefIdx;
+    if (MI->isPHI()) {
+      DefIdx = Indexes.getMBBStartIdx(MI->getParent());
+    } else {
+      DefIdx = Indexes.getInstructionIndex(MI).getRegSlot(MO.isEarlyClobber());
+    }
+    // Create the def in LR. This may find an existing def.
+    LR.createDeadDef(DefIdx, Alloc);
 }
 
-void LiveRangeCalc::createDeadDefs(LiveInterval &LI) {
+void LiveRangeCalc::calculate(LiveInterval &LI) {
   assert(MRI && Indexes && "call reset() first");
 
+  // Step 1: Create minimal live segments for every definition of Reg.
   // Visit all def operands. If the same instruction has multiple defs of Reg,
   // LR.createDeadDef() will deduplicate.
   const TargetRegisterInfo &TRI = *MRI->getTargetRegisterInfo();
   unsigned Reg = LI.reg;
-  for (const MachineOperand &MO : MRI->def_operands(Reg)) {
-    const MachineInstr *MI = MO.getParent();
-    SlotIndex Idx = getDefIndex(*Indexes, *MI, MO.isEarlyClobber());
+  for (const MachineOperand &MO : MRI->reg_nodbg_operands(Reg)) {
     unsigned SubReg = MO.getSubReg();
     if (LI.hasSubRanges() || (SubReg != 0 && MRI->tracksSubRegLiveness())) {
       unsigned Mask = SubReg != 0 ? TRI.getSubRegIndexLaneMask(SubReg)
@@ -82,155 +86,108 @@ void LiveRangeCalc::createDeadDefs(LiveInterval &LI) {
           assert(Common == S.LaneMask);
           CommonRange = &S;
         }
-        CommonRange->createDeadDef(Idx, *Alloc);
+        if (MO.isDef())
+          createDeadDef(*Indexes, *Alloc, *CommonRange, MO);
         Mask &= ~Common;
       }
+      // Create a new SubRange for subregs we did not cover yet.
       if (Mask != 0) {
-        LiveInterval::SubRange *SubRange = LI.createSubRange(*Alloc, Mask);
-        SubRange->createDeadDef(Idx, *Alloc);
+        LiveInterval::SubRange *NewRange = LI.createSubRange(*Alloc, Mask);
+        if (MO.isDef())
+          createDeadDef(*Indexes, *Alloc, *NewRange, MO);
       }
     }
 
-    // Create the def in LR. This may find an existing def.
-    LI.createDeadDef(Idx, *Alloc);
+    // Create the def in the main liverange.
+    if (MO.isDef())
+      createDeadDef(*Indexes, *Alloc, LI, MO);
   }
+
+  // Step 2: Extend live segments to all uses, constructing SSA form as
+  // necessary.
+  for (LiveInterval::SubRange &S : LI.subranges()) {
+    extendToUses(S, Reg, S.LaneMask);
+  }
+  extendToUses(LI, Reg, ~0u);
 }
 
 
-void LiveRangeCalc::createDeadDefs(LiveRange &LR, unsigned Reg) {
+void LiveRangeCalc::calculate(LiveRange &LR, unsigned Reg, bool IgnoreUses) {
   assert(MRI && Indexes && "call reset() first");
 
+  // Step 1: Create minimal live segments for every definition of Reg.
   // Visit all def operands. If the same instruction has multiple defs of Reg,
   // LR.createDeadDef() will deduplicate.
   for (MachineOperand &MO : MRI->def_operands(Reg)) {
-    const MachineInstr *MI = MO.getParent();
-    SlotIndex Idx = getDefIndex(*Indexes, *MI, MO.isEarlyClobber());
-    // Create the def in LR. This may find an existing def.
-    LR.createDeadDef(Idx, *Alloc);
+    createDeadDef(*Indexes, *Alloc, LR, MO);
   }
+
+  // Step 2: Extend live segments to all uses, constructing SSA form as
+  // necessary.
+  if (!IgnoreUses)
+    extendToUses(LR, Reg, ~0u);
 }
 
 
-static SlotIndex getUseIndex(const SlotIndexes &Indexes,
-                             const MachineOperand &MO) {
-  const MachineInstr *MI = MO.getParent();
-  unsigned OpNo = (&MO - &MI->getOperand(0));
-  if (MI->isPHI()) {
-    assert(!MO.isDef() && "Cannot handle PHI def of partial register.");
-    // The actual place where a phi operand is used is the end of the pred MBB.
-    // PHI operands are paired: (Reg, PredMBB).
-    return Indexes.getMBBEndIdx(MI->getOperand(OpNo+1).getMBB());
-  }
-
-  // Check for early-clobber redefs.
-  bool isEarlyClobber = false;
-  unsigned DefIdx;
-  if (MO.isDef()) {
-    isEarlyClobber = MO.isEarlyClobber();
-  } else if (MI->isRegTiedToDefOperand(OpNo, &DefIdx)) {
-    // FIXME: This would be a lot easier if tied early-clobber uses also
-    // had an early-clobber flag.
-    isEarlyClobber = MI->getOperand(DefIdx).isEarlyClobber();
-  }
-  return Indexes.getInstructionIndex(MI).getRegSlot(isEarlyClobber);
-}
-
-
-void LiveRangeCalc::extendToUses(LiveRange &LR, unsigned Reg) {
-  assert(MRI && Indexes && "call reset() first");
+void LiveRangeCalc::extendToUses(LiveRange &LR, unsigned Reg, unsigned Mask) {
+  unsigned NumBlocks = MF->getNumBlockIDs();
+  Seen.clear();
+  Seen.resize(NumBlocks);
+  Map.resize(NumBlocks);
 
   // Visit all operands that read Reg. This may include partial defs.
+  const TargetRegisterInfo &TRI = *MRI->getTargetRegisterInfo();
   for (MachineOperand &MO : MRI->reg_nodbg_operands(Reg)) {
     // Clear all kill flags. They will be reinserted after register allocation
     // by LiveIntervalAnalysis::addKillFlags().
     if (MO.isUse())
       MO.setIsKill(false);
-    if (!MO.readsReg())
+    // We are only interested in uses. For the main range this also includes
+    // the reads happening on partial register defs.
+    if (!MO.isUse() && (!MO.readsReg() || Mask != ~0u))
       continue;
+    unsigned SubReg = MO.getSubReg();
+    if (SubReg != 0) {
+      unsigned SubRegMask = TRI.getSubRegIndexLaneMask(SubReg);
+      // Ignore uses not covering the current subrange.
+      if ((SubRegMask & Mask) == 0)
+        continue;
+      // The create dead-defs logic in calculate() splits subranges as fine as
+      // necessary for all uses, so SubRegMask shouldn't be smaller than Mask.
+      assert((SubRegMask & ~Mask) == 0);
+    }
+
+    // Determine the actual place of the use.
+    const MachineInstr *MI = MO.getParent();
+    unsigned OpNo = (&MO - &MI->getOperand(0));
+    SlotIndex UseIdx;
+    if (MI->isPHI()) {
+      assert(!MO.isDef() && "Cannot handle PHI def of partial register.");
+      // The actual place where a phi operand is used is the end of the pred
+      // MBB. PHI operands are paired: (Reg, PredMBB).
+      UseIdx = Indexes->getMBBEndIdx(MI->getOperand(OpNo+1).getMBB());
+    } else {
+      // Check for early-clobber redefs.
+      bool isEarlyClobber = false;
+      unsigned DefIdx;
+      if (MO.isDef()) {
+        isEarlyClobber = MO.isEarlyClobber();
+      } else if (MI->isRegTiedToDefOperand(OpNo, &DefIdx)) {
+        // FIXME: This would be a lot easier if tied early-clobber uses also
+        // had an early-clobber flag.
+        isEarlyClobber = MI->getOperand(DefIdx).isEarlyClobber();
+      }
+      UseIdx = Indexes->getInstructionIndex(MI).getRegSlot(isEarlyClobber);
+    }
+
     // MI is reading Reg. We may have visited MI before if it happens to be
     // reading Reg multiple times. That is OK, extend() is idempotent.
-    SlotIndex Idx = getUseIndex(*Indexes, MO);
-    extend(LR, Idx, Reg, MainLiveOutData);
+    extend(LR, UseIdx, Reg);
   }
 }
 
 
-void LiveRangeCalc::extendToUses(LiveInterval &LI) {
-  assert(MRI && Indexes && "call reset() first");
-
-  const TargetRegisterInfo &TRI = *MRI->getTargetRegisterInfo();
-  SmallVector<LiveOutData,2> LiveOuts;
-  unsigned NumSubRanges = 0;
-  for (const auto &S : LI.subranges()) {
-    (void)S;
-    ++NumSubRanges;
-    LiveOuts.push_back(LiveOutData());
-    LiveOuts.back().reset(MF->getNumBlockIDs());
-  }
-
-  // Visit all operands that read Reg. This may include partial defs.
-  unsigned Reg = LI.reg;
-  for (MachineOperand &MO : MRI->reg_nodbg_operands(Reg)) {
-    // Clear all kill flags. They will be reinserted after register allocation
-    // by LiveIntervalAnalysis::addKillFlags().
-    if (MO.isUse())
-      MO.setIsKill(false);
-    if (!MO.readsReg())
-      continue;
-    SlotIndex Idx = getUseIndex(*Indexes, MO);
-    unsigned SubReg = MO.getSubReg();
-    if (MO.isUse() && (LI.hasSubRanges() ||
-                       (MRI->tracksSubRegLiveness() && SubReg != 0))) {
-      unsigned Mask = SubReg != 0
-        ? TRI.getSubRegIndexLaneMask(SubReg)
-        : MRI->getMaxLaneMaskForVReg(Reg);
-
-      // If this is the first time we see a subregister def/use. Initialize
-      // subranges by creating a copy of the main range.
-      if (!LI.hasSubRanges()) {
-        unsigned ClassMask = MRI->getMaxLaneMaskForVReg(Reg);
-        LI.createSubRangeFrom(*Alloc, ClassMask, LI);
-        LiveOuts.insert(LiveOuts.begin(), LiveOutData());
-        LiveOuts.front().reset(MF->getNumBlockIDs());
-        ++NumSubRanges;
-      }
-      unsigned SubRangeIdx = 0;
-      for (LiveInterval::subrange_iterator S = LI.subrange_begin(),
-           SE = LI.subrange_end(); S != SE; ++S, ++SubRangeIdx) {
-        // A Mask for subregs common to the existing subrange and current def.
-        unsigned Common = S->LaneMask & Mask;
-        if (Common == 0)
-          continue;
-        // A Mask for subregs covered by the subrange but not the current def.
-        unsigned LRest = S->LaneMask & ~Mask;
-        LiveInterval::SubRange *CommonRange;
-        unsigned CommonRangeIdx;
-        if (LRest != 0) {
-          // Split current subrange into Common and LRest ranges.
-          S->LaneMask = LRest;
-          CommonRange = LI.createSubRangeFrom(*Alloc, Common, *S);
-          CommonRangeIdx = 0;
-          LiveOuts.insert(LiveOuts.begin(), LiveOutData());
-          LiveOuts.front().reset(MF->getNumBlockIDs());
-          ++NumSubRanges;
-          ++SubRangeIdx;
-        } else {
-          // The subrange and current def lanemasks match completely.
-          assert(Common == S->LaneMask);
-          CommonRange = &*S;
-          CommonRangeIdx = SubRangeIdx;
-        }
-        extend(*CommonRange, Idx, Reg, LiveOuts[CommonRangeIdx]);
-        Mask &= ~Common;
-      }
-      assert(SubRangeIdx == NumSubRanges);
-    }
-    extend(LI, Idx, Reg, MainLiveOutData);
-  }
-}
-
-
-void LiveRangeCalc::updateFromLiveIns(LiveOutData &LiveOuts) {
+void LiveRangeCalc::updateFromLiveIns() {
   LiveRangeUpdater Updater;
   for (const LiveInBlock &I : LiveIn) {
     if (!I.DomNode)
@@ -246,8 +203,8 @@ void LiveRangeCalc::updateFromLiveIns(LiveOutData &LiveOuts) {
     else {
       // The value is live-through, update LiveOut as well.
       // Defer the Domtree lookup until it is needed.
-      assert(LiveOuts.Seen.test(MBB->getNumber()));
-      LiveOuts.Map[MBB] = LiveOutPair(I.Value, nullptr);
+      assert(Seen.test(MBB->getNumber()));
+      Map[MBB] = LiveOutPair(I.Value, nullptr);
     }
     Updater.setDest(&I.LR);
     Updater.add(Start, End, I.Value);
@@ -256,8 +213,7 @@ void LiveRangeCalc::updateFromLiveIns(LiveOutData &LiveOuts) {
 }
 
 
-void LiveRangeCalc::extend(LiveRange &LR, SlotIndex Kill, unsigned PhysReg,
-                           LiveOutData &LiveOuts) {
+void LiveRangeCalc::extend(LiveRange &LR, SlotIndex Kill, unsigned PhysReg) {
   assert(Kill.isValid() && "Invalid SlotIndex");
   assert(Indexes && "Missing SlotIndexes");
   assert(DomTree && "Missing dominator tree");
@@ -273,28 +229,27 @@ void LiveRangeCalc::extend(LiveRange &LR, SlotIndex Kill, unsigned PhysReg,
   // multiple values, and we may need to create even more phi-defs to preserve
   // VNInfo SSA form.  Perform a search for all predecessor blocks where we
   // know the dominating VNInfo.
-  if (findReachingDefs(LR, *KillMBB, Kill, PhysReg, LiveOuts))
+  if (findReachingDefs(LR, *KillMBB, Kill, PhysReg))
     return;
 
   // When there were multiple different values, we may need new PHIs.
-  calculateValues(LiveOuts);
+  calculateValues();
 }
 
 
 // This function is called by a client after using the low-level API to add
 // live-out and live-in blocks.  The unique value optimization is not
 // available, SplitEditor::transferValues handles that case directly anyway.
-void LiveRangeCalc::calculateValues(LiveOutData &LiveOuts) {
+void LiveRangeCalc::calculateValues() {
   assert(Indexes && "Missing SlotIndexes");
   assert(DomTree && "Missing dominator tree");
-  updateSSA(LiveOuts);
-  updateFromLiveIns(LiveOuts);
+  updateSSA();
+  updateFromLiveIns();
 }
 
 
 bool LiveRangeCalc::findReachingDefs(LiveRange &LR, MachineBasicBlock &KillMBB,
-                                     SlotIndex Kill, unsigned PhysReg,
-                                     LiveOutData &LiveOuts) {
+                                     SlotIndex Kill, unsigned PhysReg) {
   unsigned KillMBBNum = KillMBB.getNumber();
 
   // Block numbers where LR should be live-in.
@@ -328,8 +283,8 @@ bool LiveRangeCalc::findReachingDefs(LiveRange &LR, MachineBasicBlock &KillMBB,
        MachineBasicBlock *Pred = *PI;
 
        // Is this a known live-out block?
-       if (LiveOuts.Seen.test(Pred->getNumber())) {
-         if (VNInfo *VNI = LiveOuts.Map[Pred].first) {
+       if (Seen.test(Pred->getNumber())) {
+         if (VNInfo *VNI = Map[Pred].first) {
            if (TheVNI && TheVNI != VNI)
              UniqueVNI = false;
            TheVNI = VNI;
@@ -343,7 +298,7 @@ bool LiveRangeCalc::findReachingDefs(LiveRange &LR, MachineBasicBlock &KillMBB,
        // First time we see Pred.  Try to determine the live-out value, but set
        // it as null if Pred is live-through with an unknown value.
        VNInfo *VNI = LR.extendInBlock(Start, End);
-       LiveOuts.setLiveOutValue(Pred, VNI);
+       setLiveOutValue(Pred, VNI);
        if (VNI) {
          if (TheVNI && TheVNI != VNI)
            UniqueVNI = false;
@@ -378,8 +333,7 @@ bool LiveRangeCalc::findReachingDefs(LiveRange &LR, MachineBasicBlock &KillMBB,
        if (*I == KillMBBNum && Kill.isValid())
          End = Kill;
        else
-         LiveOuts.Map[MF->getBlockNumbered(*I)] =
-           LiveOutPair(TheVNI, nullptr);
+         Map[MF->getBlockNumbered(*I)] = LiveOutPair(TheVNI, nullptr);
        Updater.add(Start, End, TheVNI);
     }
     return true;
@@ -402,7 +356,7 @@ bool LiveRangeCalc::findReachingDefs(LiveRange &LR, MachineBasicBlock &KillMBB,
 
 // This is essentially the same iterative algorithm that SSAUpdater uses,
 // except we already have a dominator tree, so we don't have to recompute it.
-void LiveRangeCalc::updateSSA(LiveOutData &LiveOuts) {
+void LiveRangeCalc::updateSSA() {
   assert(Indexes && "Missing SlotIndexes");
   assert(DomTree && "Missing dominator tree");
 
@@ -423,23 +377,22 @@ void LiveRangeCalc::updateSSA(LiveOutData &LiveOuts) {
 
       // We need a live-in value to a block with no immediate dominator?
       // This is probably an unreachable block that has survived somehow.
-      bool needPHI = !IDom
-                  || !LiveOuts.Seen.test(IDom->getBlock()->getNumber());
+      bool needPHI = !IDom || !Seen.test(IDom->getBlock()->getNumber());
 
       // IDom dominates all of our predecessors, but it may not be their
       // immediate dominator. Check if any of them have live-out values that are
       // properly dominated by IDom. If so, we need a phi-def here.
       if (!needPHI) {
-        IDomValue = LiveOuts.Map[IDom->getBlock()];
+        IDomValue = Map[IDom->getBlock()];
 
         // Cache the DomTree node that defined the value.
         if (IDomValue.first && !IDomValue.second)
-          LiveOuts.Map[IDom->getBlock()].second = IDomValue.second =
+          Map[IDom->getBlock()].second = IDomValue.second =
             DomTree->getNode(Indexes->getMBBFromIndex(IDomValue.first->def));
 
         for (MachineBasicBlock::pred_iterator PI = MBB->pred_begin(),
                PE = MBB->pred_end(); PI != PE; ++PI) {
-          LiveOutPair &Value = LiveOuts.Map[*PI];
+          LiveOutPair &Value = Map[*PI];
           if (!Value.first || Value.first == IDomValue.first)
             continue;
 
@@ -461,7 +414,7 @@ void LiveRangeCalc::updateSSA(LiveOutData &LiveOuts) {
       // The value may be live-through even if Kill is set, as can happen when
       // we are called from extendRange. In that case LiveOutSeen is true, and
       // LiveOut indicates a foreign or missing value.
-      LiveOutPair &LOP = LiveOuts.Map[MBB];
+      LiveOutPair &LOP = Map[MBB];
 
       // Create a phi-def if required.
       if (needPHI) {
diff --git a/lib/CodeGen/LiveRangeCalc.h b/lib/CodeGen/LiveRangeCalc.h
index fd494797918..913d09edbdd 100644
--- a/lib/CodeGen/LiveRangeCalc.h
+++ b/lib/CodeGen/LiveRangeCalc.h
@@ -47,44 +47,30 @@ class LiveRangeCalc {
   /// LiveOutMap - Map basic blocks to the value leaving the block.
   typedef IndexedMap<LiveOutPair, MBB2NumberFunctor> LiveOutMap;
 
-  struct LiveOutData {
-    /// Seen - Bit vector of active entries in LiveOut, also used as a visited
-    /// set by findReachingDefs.  One entry per basic block, indexed by block
-    /// number.  This is kept as a separate bit vector because it can be cleared
-    /// quickly when switching live ranges.
-    BitVector Seen;
+  /// Seen - Bit vector of active entries in LiveOut, also used as a visited
+  /// set by findReachingDefs.  One entry per basic block, indexed by block
+  /// number.  This is kept as a separate bit vector because it can be cleared
+  /// quickly when switching live ranges.
+  BitVector Seen;
 
-    /// LiveOut - Map each basic block where a live range is live out to the
-    /// live-out value and its defining block.
-    ///
-    /// For every basic block, MBB, one of these conditions shall be true:
-    ///
-    ///  1. !Seen.count(MBB->getNumber())
-    ///     Blocks without a Seen bit are ignored.
-    ///  2. LiveOut[MBB].second.getNode() == MBB
-    ///     The live-out value is defined in MBB.
-    ///  3. forall P in preds(MBB): LiveOut[P] == LiveOut[MBB]
-    ///     The live-out value passses through MBB. All predecessors must carry
-    ///     the same value.
-    ///
-    /// The domtree node may be null, it can be computed.
-    ///
-    /// The map can be shared by multiple live ranges as long as no two are
-    /// live-out of the same block.
-    LiveOutMap Map;
-
-    void reset(unsigned NumBlocks) {
-      Seen.clear();
-      Seen.resize(NumBlocks);
-      Map.resize(NumBlocks);
-    }
-
-    void setLiveOutValue(MachineBasicBlock *MBB, VNInfo *VNI) {
-      Seen.set(MBB->getNumber());
-      Map[MBB] = LiveOutPair(VNI, nullptr);
-    }
-  };
-  LiveOutData MainLiveOutData;
+  /// LiveOut - Map each basic block where a live range is live out to the
+  /// live-out value and its defining block.
+  ///
+  /// For every basic block, MBB, one of these conditions shall be true:
+  ///
+  ///  1. !Seen.count(MBB->getNumber())
+  ///     Blocks without a Seen bit are ignored.
+  ///  2. LiveOut[MBB].second.getNode() == MBB
+  ///     The live-out value is defined in MBB.
+  ///  3. forall P in preds(MBB): LiveOut[P] == LiveOut[MBB]
+  ///     The live-out value passses through MBB. All predecessors must carry
+  ///     the same value.
+  ///
+  /// The domtree node may be null, it can be computed.
+  ///
+  /// The map can be shared by multiple live ranges as long as no two are
+  /// live-out of the same block.
+  LiveOutMap Map;
 
   /// LiveInBlock - Information about a basic block where a live range is known
   /// to be live-in, but the value has not yet been determined.
@@ -126,19 +112,24 @@ class LiveRangeCalc {
   ///
   /// PhysReg, when set, is used to verify live-in lists on basic blocks.
   bool findReachingDefs(LiveRange &LR, MachineBasicBlock &KillMBB,
-                        SlotIndex Kill, unsigned PhysReg,
-                        LiveOutData &LiveOuts);
+                        SlotIndex Kill, unsigned PhysReg);
 
   /// updateSSA - Compute the values that will be live in to all requested
   /// blocks in LiveIn.  Create PHI-def values as required to preserve SSA form.
   ///
   /// Every live-in block must be jointly dominated by the added live-out
   /// blocks.  No values are read from the live ranges.
-  void updateSSA(LiveOutData &LiveOuts);
+  void updateSSA();
 
   /// Transfer information from the LiveIn vector to the live ranges and update
   /// the given @p LiveOuts.
-  void updateFromLiveIns(LiveOutData &LiveOuts);
+  void updateFromLiveIns();
+
+  /// Extend the live range of @p LR to reach all uses of Reg.
+  ///
+  /// All uses must be jointly dominated by existing liveness.  PHI-defs are
+  /// inserted as needed to preserve SSA form.
+  void extendToUses(LiveRange &LR, unsigned Reg, unsigned LaneMask = ~0u);
 
 public:
   LiveRangeCalc() : MF(nullptr), MRI(nullptr), Indexes(nullptr),
@@ -176,39 +167,16 @@ public:
   /// single existing value, Alloc may be null.
   ///
   /// PhysReg, when set, is used to verify live-in lists on basic blocks.
-  void extend(LiveRange &LR, SlotIndex Kill, unsigned PhysReg,
-              LiveOutData &LiveOuts);
+  void extend(LiveRange &LR, SlotIndex Kill, unsigned PhysReg = 0);
 
-  void extend(LiveRange &LR, SlotIndex Kill) {
-    extend(LR, Kill, 0, MainLiveOutData);
-  }
+  /// Calculates liveness for the uses/defs of a given registers.  The results
+  /// are written to @p LR.
+  void calculate(LiveRange &LR, unsigned Reg, bool IgnoreUses);
 
-  /// createDeadDefs - Create a dead def in LI for every def operand of Reg.
-  /// Each instruction defining Reg gets a new VNInfo with a corresponding
-  /// minimal live range.
-  void createDeadDefs(LiveRange &LR, unsigned Reg);
-
-  /// Subregister aware version of createDeadDefs(LiveRange &LR, unsigned Reg).
-  /// If subregister liveness tracking is enabled new subranges are created as
-  /// necessary when subregister defs are found. As with
-  /// createDeadDefs(LiveRange &LR, unsigned Reg) new short live segments are
-  /// created for every def of LI.reg. The new segments start and end at the
-  /// defining instruction (hence the name "DeadDef").
-  void createDeadDefs(LiveInterval &LI);
-
-  /// extendToUses - Extend the live range of LI to reach all uses of Reg.
-  ///
-  /// All uses must be jointly dominated by existing liveness.  PHI-defs are
-  /// inserted as needed to preserve SSA form.
-  void extendToUses(LiveRange &LR, unsigned Reg);
-
-  /// Subregister aware version of extendToUses(LiveRange &LR, unsigned Reg).
-  /// If subregister liveness tracking is enabled new subranges are created
-  /// as necessary when subregister uses are found. As with
-  /// extendToUses(LiveRange &LR, unsigned Reg) the segments existing at the
-  /// defs are extend until they reach all uses. New value numbers are created
-  /// at CFG joins as necessary (SSA construction).
-  void extendToUses(LiveInterval &LI);
+  /// Calculates liveness for the register specified in live interval @p LI.
+  /// Creates subregister live ranges as needed if subreg liveness tracking is
+  /// enabled.
+  void calculate(LiveInterval &LI);
 
   //===--------------------------------------------------------------------===//
   // Low-level interface.
@@ -230,7 +198,8 @@ public:
   /// VNI may be null only if MBB is a live-through block also passed to
   /// addLiveInBlock().
   void setLiveOutValue(MachineBasicBlock *MBB, VNInfo *VNI) {
-    MainLiveOutData.setLiveOutValue(MBB, VNI);
+    Seen.set(MBB->getNumber());
+    Map[MBB] = LiveOutPair(VNI, nullptr);
   }
 
   /// addLiveInBlock - Add a block with an unknown live-in value.  This
@@ -255,11 +224,7 @@ public:
   ///
   /// Every predecessor of a live-in block must have been given a value with
   /// setLiveOutValue, the value may be null for live-trough blocks.
-  void calculateValues(LiveOutData &LiveOuts);
-
-  void calculateValues() {
-    calculateValues(MainLiveOutData);
-  }
+  void calculateValues();
 };
 
 } // end namespace llvm