mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-07-19 03:29:22 +00:00
Reorg. No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28999 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng
parent
d8122c3dff
commit
60c07e1aea
@ -1394,139 +1394,6 @@ static bool hasFPCMov(unsigned X86CC) {
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}
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}
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MachineBasicBlock *
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X86TargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI,
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MachineBasicBlock *BB) {
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switch (MI->getOpcode()) {
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default: assert(false && "Unexpected instr type to insert");
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case X86::CMOV_FR32:
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case X86::CMOV_FR64:
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case X86::CMOV_V4F32:
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case X86::CMOV_V2F64:
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case X86::CMOV_V2I64: {
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// To "insert" a SELECT_CC instruction, we actually have to insert the
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// diamond control-flow pattern. The incoming instruction knows the
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// destination vreg to set, the condition code register to branch on, the
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// true/false values to select between, and a branch opcode to use.
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const BasicBlock *LLVM_BB = BB->getBasicBlock();
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ilist<MachineBasicBlock>::iterator It = BB;
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++It;
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// thisMBB:
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// ...
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// TrueVal = ...
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// cmpTY ccX, r1, r2
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// bCC copy1MBB
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// fallthrough --> copy0MBB
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MachineBasicBlock *thisMBB = BB;
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MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB);
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MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB);
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unsigned Opc = getCondBrOpcodeForX86CC(MI->getOperand(3).getImmedValue());
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BuildMI(BB, Opc, 1).addMBB(sinkMBB);
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MachineFunction *F = BB->getParent();
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F->getBasicBlockList().insert(It, copy0MBB);
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F->getBasicBlockList().insert(It, sinkMBB);
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// Update machine-CFG edges by first adding all successors of the current
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// block to the new block which will contain the Phi node for the select.
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for(MachineBasicBlock::succ_iterator i = BB->succ_begin(),
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e = BB->succ_end(); i != e; ++i)
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sinkMBB->addSuccessor(*i);
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// Next, remove all successors of the current block, and add the true
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// and fallthrough blocks as its successors.
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while(!BB->succ_empty())
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BB->removeSuccessor(BB->succ_begin());
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BB->addSuccessor(copy0MBB);
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BB->addSuccessor(sinkMBB);
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// copy0MBB:
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// %FalseValue = ...
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// # fallthrough to sinkMBB
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BB = copy0MBB;
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// Update machine-CFG edges
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BB->addSuccessor(sinkMBB);
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// sinkMBB:
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// %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
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// ...
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BB = sinkMBB;
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BuildMI(BB, X86::PHI, 4, MI->getOperand(0).getReg())
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.addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
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.addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
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delete MI; // The pseudo instruction is gone now.
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return BB;
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}
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case X86::FP_TO_INT16_IN_MEM:
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case X86::FP_TO_INT32_IN_MEM:
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case X86::FP_TO_INT64_IN_MEM: {
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// Change the floating point control register to use "round towards zero"
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// mode when truncating to an integer value.
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MachineFunction *F = BB->getParent();
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int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2);
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addFrameReference(BuildMI(BB, X86::FNSTCW16m, 4), CWFrameIdx);
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// Load the old value of the high byte of the control word...
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unsigned OldCW =
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F->getSSARegMap()->createVirtualRegister(X86::GR16RegisterClass);
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addFrameReference(BuildMI(BB, X86::MOV16rm, 4, OldCW), CWFrameIdx);
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// Set the high part to be round to zero...
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addFrameReference(BuildMI(BB, X86::MOV16mi, 5), CWFrameIdx).addImm(0xC7F);
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// Reload the modified control word now...
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addFrameReference(BuildMI(BB, X86::FLDCW16m, 4), CWFrameIdx);
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// Restore the memory image of control word to original value
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addFrameReference(BuildMI(BB, X86::MOV16mr, 5), CWFrameIdx).addReg(OldCW);
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// Get the X86 opcode to use.
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unsigned Opc;
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switch (MI->getOpcode()) {
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default: assert(0 && "illegal opcode!");
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case X86::FP_TO_INT16_IN_MEM: Opc = X86::FpIST16m; break;
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case X86::FP_TO_INT32_IN_MEM: Opc = X86::FpIST32m; break;
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case X86::FP_TO_INT64_IN_MEM: Opc = X86::FpIST64m; break;
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}
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X86AddressMode AM;
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MachineOperand &Op = MI->getOperand(0);
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if (Op.isRegister()) {
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AM.BaseType = X86AddressMode::RegBase;
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AM.Base.Reg = Op.getReg();
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} else {
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AM.BaseType = X86AddressMode::FrameIndexBase;
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AM.Base.FrameIndex = Op.getFrameIndex();
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}
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Op = MI->getOperand(1);
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if (Op.isImmediate())
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AM.Scale = Op.getImmedValue();
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Op = MI->getOperand(2);
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if (Op.isImmediate())
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AM.IndexReg = Op.getImmedValue();
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Op = MI->getOperand(3);
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if (Op.isGlobalAddress()) {
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AM.GV = Op.getGlobal();
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} else {
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AM.Disp = Op.getImmedValue();
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}
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addFullAddress(BuildMI(BB, Opc, 5), AM).addReg(MI->getOperand(4).getReg());
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// Reload the original control word now.
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addFrameReference(BuildMI(BB, X86::FLDCW16m, 4), CWFrameIdx);
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delete MI; // The pseudo instruction is gone now.
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return BB;
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}
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}
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}
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//===----------------------------------------------------------------------===//
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// X86 Custom Lowering Hooks
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//===----------------------------------------------------------------------===//
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/// DarwinGVRequiresExtraLoad - true if accessing the GV requires an extra
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/// load. For Darwin, external and weak symbols are indirect, loading the value
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/// at address GV rather then the value of GV itself. This means that the
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@ -3892,6 +3759,197 @@ const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
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}
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}
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/// isLegalAddressImmediate - Return true if the integer value or
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/// GlobalValue can be used as the offset of the target addressing mode.
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bool X86TargetLowering::isLegalAddressImmediate(int64_t V) const {
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// X86 allows a sign-extended 32-bit immediate field.
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return (V > -(1LL << 32) && V < (1LL << 32)-1);
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}
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bool X86TargetLowering::isLegalAddressImmediate(GlobalValue *GV) const {
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// GV is 64-bit but displacement field is 32-bit unless we are in small code
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// model. Mac OS X happens to support only small PIC code model.
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// FIXME: better support for other OS's.
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if (Subtarget->is64Bit() && !Subtarget->isTargetDarwin())
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return false;
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if (Subtarget->isTargetDarwin()) {
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Reloc::Model RModel = getTargetMachine().getRelocationModel();
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if (RModel == Reloc::Static)
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return true;
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else if (RModel == Reloc::DynamicNoPIC)
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return !DarwinGVRequiresExtraLoad(GV);
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else
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return false;
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} else
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return true;
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}
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/// isShuffleMaskLegal - Targets can use this to indicate that they only
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/// support *some* VECTOR_SHUFFLE operations, those with specific masks.
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/// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
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/// are assumed to be legal.
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bool
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X86TargetLowering::isShuffleMaskLegal(SDOperand Mask, MVT::ValueType VT) const {
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// Only do shuffles on 128-bit vector types for now.
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if (MVT::getSizeInBits(VT) == 64) return false;
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return (Mask.Val->getNumOperands() <= 4 ||
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isSplatMask(Mask.Val) ||
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isPSHUFHW_PSHUFLWMask(Mask.Val) ||
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X86::isUNPCKLMask(Mask.Val) ||
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X86::isUNPCKL_v_undef_Mask(Mask.Val) ||
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X86::isUNPCKHMask(Mask.Val));
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}
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bool X86TargetLowering::isVectorClearMaskLegal(std::vector<SDOperand> &BVOps,
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MVT::ValueType EVT,
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SelectionDAG &DAG) const {
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unsigned NumElts = BVOps.size();
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// Only do shuffles on 128-bit vector types for now.
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if (MVT::getSizeInBits(EVT) * NumElts == 64) return false;
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if (NumElts == 2) return true;
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if (NumElts == 4) {
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return (isMOVLMask(BVOps) || isCommutedMOVL(BVOps, true) ||
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isSHUFPMask(BVOps) || isCommutedSHUFP(BVOps));
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}
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return false;
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}
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//===----------------------------------------------------------------------===//
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// X86 Scheduler Hooks
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//===----------------------------------------------------------------------===//
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MachineBasicBlock *
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X86TargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI,
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MachineBasicBlock *BB) {
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switch (MI->getOpcode()) {
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default: assert(false && "Unexpected instr type to insert");
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case X86::CMOV_FR32:
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case X86::CMOV_FR64:
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case X86::CMOV_V4F32:
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case X86::CMOV_V2F64:
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case X86::CMOV_V2I64: {
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// To "insert" a SELECT_CC instruction, we actually have to insert the
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// diamond control-flow pattern. The incoming instruction knows the
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// destination vreg to set, the condition code register to branch on, the
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// true/false values to select between, and a branch opcode to use.
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const BasicBlock *LLVM_BB = BB->getBasicBlock();
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ilist<MachineBasicBlock>::iterator It = BB;
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++It;
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// thisMBB:
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// ...
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// TrueVal = ...
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// cmpTY ccX, r1, r2
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// bCC copy1MBB
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// fallthrough --> copy0MBB
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MachineBasicBlock *thisMBB = BB;
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MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB);
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MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB);
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unsigned Opc = getCondBrOpcodeForX86CC(MI->getOperand(3).getImmedValue());
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BuildMI(BB, Opc, 1).addMBB(sinkMBB);
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MachineFunction *F = BB->getParent();
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F->getBasicBlockList().insert(It, copy0MBB);
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F->getBasicBlockList().insert(It, sinkMBB);
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// Update machine-CFG edges by first adding all successors of the current
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// block to the new block which will contain the Phi node for the select.
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for(MachineBasicBlock::succ_iterator i = BB->succ_begin(),
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e = BB->succ_end(); i != e; ++i)
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sinkMBB->addSuccessor(*i);
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// Next, remove all successors of the current block, and add the true
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// and fallthrough blocks as its successors.
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while(!BB->succ_empty())
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BB->removeSuccessor(BB->succ_begin());
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BB->addSuccessor(copy0MBB);
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BB->addSuccessor(sinkMBB);
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// copy0MBB:
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// %FalseValue = ...
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// # fallthrough to sinkMBB
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BB = copy0MBB;
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// Update machine-CFG edges
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BB->addSuccessor(sinkMBB);
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// sinkMBB:
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// %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
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// ...
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BB = sinkMBB;
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BuildMI(BB, X86::PHI, 4, MI->getOperand(0).getReg())
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.addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
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.addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
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delete MI; // The pseudo instruction is gone now.
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return BB;
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}
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case X86::FP_TO_INT16_IN_MEM:
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case X86::FP_TO_INT32_IN_MEM:
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case X86::FP_TO_INT64_IN_MEM: {
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// Change the floating point control register to use "round towards zero"
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// mode when truncating to an integer value.
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MachineFunction *F = BB->getParent();
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int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2);
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addFrameReference(BuildMI(BB, X86::FNSTCW16m, 4), CWFrameIdx);
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// Load the old value of the high byte of the control word...
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unsigned OldCW =
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F->getSSARegMap()->createVirtualRegister(X86::GR16RegisterClass);
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addFrameReference(BuildMI(BB, X86::MOV16rm, 4, OldCW), CWFrameIdx);
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// Set the high part to be round to zero...
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addFrameReference(BuildMI(BB, X86::MOV16mi, 5), CWFrameIdx).addImm(0xC7F);
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// Reload the modified control word now...
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addFrameReference(BuildMI(BB, X86::FLDCW16m, 4), CWFrameIdx);
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// Restore the memory image of control word to original value
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addFrameReference(BuildMI(BB, X86::MOV16mr, 5), CWFrameIdx).addReg(OldCW);
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// Get the X86 opcode to use.
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unsigned Opc;
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switch (MI->getOpcode()) {
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default: assert(0 && "illegal opcode!");
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case X86::FP_TO_INT16_IN_MEM: Opc = X86::FpIST16m; break;
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case X86::FP_TO_INT32_IN_MEM: Opc = X86::FpIST32m; break;
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case X86::FP_TO_INT64_IN_MEM: Opc = X86::FpIST64m; break;
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}
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X86AddressMode AM;
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MachineOperand &Op = MI->getOperand(0);
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if (Op.isRegister()) {
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AM.BaseType = X86AddressMode::RegBase;
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AM.Base.Reg = Op.getReg();
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} else {
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AM.BaseType = X86AddressMode::FrameIndexBase;
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AM.Base.FrameIndex = Op.getFrameIndex();
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}
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Op = MI->getOperand(1);
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if (Op.isImmediate())
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AM.Scale = Op.getImmedValue();
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Op = MI->getOperand(2);
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if (Op.isImmediate())
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AM.IndexReg = Op.getImmedValue();
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Op = MI->getOperand(3);
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if (Op.isGlobalAddress()) {
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AM.GV = Op.getGlobal();
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} else {
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AM.Disp = Op.getImmedValue();
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}
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addFullAddress(BuildMI(BB, Opc, 5), AM).addReg(MI->getOperand(4).getReg());
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// Reload the original control word now.
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addFrameReference(BuildMI(BB, X86::FLDCW16m, 4), CWFrameIdx);
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delete MI; // The pseudo instruction is gone now.
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return BB;
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}
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}
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}
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//===----------------------------------------------------------------------===//
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// X86 Optimization Hooks
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//===----------------------------------------------------------------------===//
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void X86TargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op,
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uint64_t Mask,
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uint64_t &KnownZero,
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@ -3914,6 +3972,10 @@ void X86TargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op,
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}
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}
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//===----------------------------------------------------------------------===//
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// X86 Inline Assembly Support
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//===----------------------------------------------------------------------===//
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std::vector<unsigned> X86TargetLowering::
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getRegClassForInlineAsmConstraint(const std::string &Constraint,
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MVT::ValueType VT) const {
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@ -3969,53 +4031,3 @@ getRegClassForInlineAsmConstraint(const std::string &Constraint,
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return std::vector<unsigned>();
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}
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/// isLegalAddressImmediate - Return true if the integer value or
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/// GlobalValue can be used as the offset of the target addressing mode.
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bool X86TargetLowering::isLegalAddressImmediate(int64_t V) const {
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// X86 allows a sign-extended 32-bit immediate field.
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return (V > -(1LL << 32) && V < (1LL << 32)-1);
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}
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bool X86TargetLowering::isLegalAddressImmediate(GlobalValue *GV) const {
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if (Subtarget->isTargetDarwin()) {
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Reloc::Model RModel = getTargetMachine().getRelocationModel();
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if (RModel == Reloc::Static)
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return true;
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else if (RModel == Reloc::DynamicNoPIC)
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return !DarwinGVRequiresExtraLoad(GV);
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else
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return false;
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} else
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return true;
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}
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/// isShuffleMaskLegal - Targets can use this to indicate that they only
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/// support *some* VECTOR_SHUFFLE operations, those with specific masks.
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/// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
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/// are assumed to be legal.
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bool
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X86TargetLowering::isShuffleMaskLegal(SDOperand Mask, MVT::ValueType VT) const {
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// Only do shuffles on 128-bit vector types for now.
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if (MVT::getSizeInBits(VT) == 64) return false;
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return (Mask.Val->getNumOperands() <= 4 ||
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isSplatMask(Mask.Val) ||
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isPSHUFHW_PSHUFLWMask(Mask.Val) ||
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X86::isUNPCKLMask(Mask.Val) ||
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X86::isUNPCKL_v_undef_Mask(Mask.Val) ||
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X86::isUNPCKHMask(Mask.Val));
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}
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bool X86TargetLowering::isVectorClearMaskLegal(std::vector<SDOperand> &BVOps,
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MVT::ValueType EVT,
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SelectionDAG &DAG) const {
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unsigned NumElts = BVOps.size();
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// Only do shuffles on 128-bit vector types for now.
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if (MVT::getSizeInBits(EVT) * NumElts == 64) return false;
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if (NumElts == 2) return true;
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if (NumElts == 4) {
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return (isMOVLMask(BVOps) || isCommutedMOVL(BVOps, true) ||
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isSHUFPMask(BVOps) || isCommutedSHUFP(BVOps));
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}
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return false;
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}
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