6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-02-19 06:31:18 +00:00
Code Issues Projects Releases Wiki Activity

Fix disassembly of some VST1 instructions.

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143507 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Owen Anderson 2011-11-01 22:18:13 +00:00
parent 0173864d8a
commit 60cb643f75
2 changed files with 21 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

24
lib/Target/ARM/Disassembler/ARMDisassembler.cpp
View File

@ -2240,13 +2240,27 @@ static DecodeStatus DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Insn,
return MCDisassembler::Fail; return MCDisassembler::Fail;
// AddrMode6 Offset (register) // AddrMode6 Offset (register)
if (Rm == 0xD) switch (Inst.getOpcode()) {
Inst.addOperand(MCOperand::CreateReg(0)); default:
else if (Rm != 0xF) { if (Rm == 0xD)
if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) Inst.addOperand(MCOperand::CreateReg(0));
return MCDisassembler::Fail; else if (Rm != 0xF) {
if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
return MCDisassembler::Fail;
}
break;
case ARM::VST1d8wb_fixed:
case ARM::VST1d16wb_fixed:
case ARM::VST1d32wb_fixed:
case ARM::VST1d64wb_fixed:
case ARM::VST1q8wb_fixed:
case ARM::VST1q16wb_fixed:
case ARM::VST1q32wb_fixed:
case ARM::VST1q64wb_fixed:
break;
} }
// First input register // First input register
if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;

3
test/MC/Disassembler/ARM/neon.txt
View File

@ -1861,4 +1861,5 @@
# CHECK: vld1.8 {d23, d24, d25}, [r6, :64]! # CHECK: vld1.8 {d23, d24, d25}, [r6, :64]!
0x9d 0x62 0x6f 0xf4 0x9d 0x62 0x6f 0xf4
# CHECK: vld1.32 {d22, d23, d24, d25}, [pc, :64]! # CHECK: vld1.32 {d22, d23, d24, d25}, [pc, :64]!
0x9d 0xaa 0x41 0xf4
# CHECK: vst1.32 {d26, d27}, [r1, :64]!