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Truncate the immediate in logical operation to the register width

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And continue to produce an error if the 32 most significant bits are not all ones or zeros.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212520 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Arnaud A. de Grandmaison 2014-07-08 09:53:04 +00:00
parent ffbc2a1325
commit 60d8767211
3 changed files with 39 additions and 2 deletions
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9
lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
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@ -619,7 +619,11 @@ public:
const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(getImm());
if (!MCE)
return false;
return AArch64_AM::isLogicalImmediate(MCE->getValue(), 32);
int64_t Val = MCE->getValue();
if (Val >> 32 != 0 && Val >> 32 != ~0LL)
return false;
Val &= 0xFFFFFFFF;
return AArch64_AM::isLogicalImmediate(Val, 32);
}
bool isLogicalImm64() const {
if (!isImm())
@ -1360,7 +1364,8 @@ public:
assert(N == 1 && "Invalid number of operands!");
const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(getImm());
assert(MCE && "Invalid logical immediate operand!");
uint64_t encoding = AArch64_AM::encodeLogicalImmediate(MCE->getValue(), 32);
uint64_t encoding =
AArch64_AM::encodeLogicalImmediate(MCE->getValue() & 0xFFFFFFFF, 32);
Inst.addOperand(MCOperand::CreateImm(encoding));
}

21
test/MC/AArch64/basic-a64-diagnostics.s
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@ -728,6 +728,27 @@
// CHECK-ERROR-NEXT: ngcs x2, sp
// CHECK-ERROR-NEXT: ^
//------------------------------------------------------------------------------
// Logical (immediates)
//------------------------------------------------------------------------------
and w2, w3, #4294967296
eor w2, w3, #4294967296
orr w2, w3, #4294967296
ands w2, w3, #4294967296
// CHECK-ERROR: error: expected compatible register or logical immediate
// CHECK-ERROR-NEXT: and w2, w3, #4294967296
// CHECK-ERROR-NEXT: ^
// CHECK-ERROR-NEXT: error: expected compatible register or logical immediate
// CHECK-ERROR-NEXT: eor w2, w3, #4294967296
// CHECK-ERROR-NEXT: ^
// CHECK-ERROR-NEXT: error: expected compatible register or logical immediate
// CHECK-ERROR-NEXT: orr w2, w3, #4294967296
// CHECK-ERROR-NEXT: ^
// CHECK-ERROR-NEXT: error: expected compatible register or logical immediate
// CHECK-ERROR-NEXT: ands w2, w3, #4294967296
// CHECK-ERROR-NEXT: ^
//------------------------------------------------------------------------------
// Bitfield
//------------------------------------------------------------------------------

11
test/MC/AArch64/basic-a64-instructions.s
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@ -3245,6 +3245,17 @@ _func:
// CHECK: orr w3, wzr, #0xf000f // encoding: [0xe3,0x8f,0x00,0x32]
// CHECK: orr x10, xzr, #0xaaaaaaaaaaaaaaaa // encoding: [0xea,0xf3,0x01,0xb2]
// The Imm field of logicalImm operations has to be truncated to the
// register width, i.e. 32 bits
and w2, w3, #-3
orr w0, w1, #~2
eor w16, w17, #-7
ands w19, w20, #~15
// CHECK: and w2, w3, #0xfffffffd // encoding: [0x62,0x78,0x1e,0x12]
// CHECK: orr w0, w1, #0xfffffffd // encoding: [0x20,0x78,0x1e,0x32]
// CHECK: eor w16, w17, #0xfffffff9 // encoding: [0x30,0x76,0x1d,0x52]
// CHECK: ands w19, w20, #0xfffffff0 // encoding: [0x93,0x6e,0x1c,0x72]
//------------------------------------------------------------------------------
// Logical (shifted register)
//------------------------------------------------------------------------------