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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174852 91177308-0d34-0410-b5e6-96231b3b80d8
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Joel Jones 2013-02-10 23:56:30 +00:00
parent f5844a7515
commit 612779eb83
1 changed files with 1 additions and 1 deletions
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lib/Target/AArch64/AArch64ISelLowering.cpp
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@ -2691,7 +2691,7 @@ static bool findEXTRHalf(SDValue N, SDValue &Src, uint32_t &ShiftAmount,
return true;
}
/// EXTR instruciton extracts a contiguous chunk of bits from two existing
/// EXTR instruction extracts a contiguous chunk of bits from two existing
/// registers viewed as a high/low pair. This function looks for the pattern:
/// (or (shl VAL1, #N), (srl VAL2, #RegWidth-N)) and replaces it with an
/// EXTR. Can't quite be done in TableGen because the two immediates aren't