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RegisterPressure heuristics currently require signed comparisons.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178823 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Andrew Trick
2013-04-05 00:31:34 +00:00
parent 2182977ff2
commit 614dacc910
2 changed files with 230 additions and 2 deletions
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4
lib/CodeGen/MachineScheduler.cpp
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@ -1660,7 +1660,7 @@ initResourceDelta(const ScheduleDAGMI *DAG,
}
/// Return true if this heuristic determines order.
static bool tryLess(unsigned TryVal, unsigned CandVal,
static bool tryLess(int TryVal, int CandVal,
ConvergingScheduler::SchedCandidate &TryCand,
ConvergingScheduler::SchedCandidate &Cand,
ConvergingScheduler::CandReason Reason) {
@ -1676,7 +1676,7 @@ static bool tryLess(unsigned TryVal, unsigned CandVal,
return false;
}
static bool tryGreater(unsigned TryVal, unsigned CandVal,
static bool tryGreater(int TryVal, int CandVal,
ConvergingScheduler::SchedCandidate &TryCand,
ConvergingScheduler::SchedCandidate &Cand,
ConvergingScheduler::CandReason Reason) {