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Teach MachineLICM reg pressure tracking code to deal with MVT::untyped. Sorry, I can't come up with a small test case. rdar://10043690
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138934 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -202,6 +202,13 @@ namespace {
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///
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///
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void HoistRegion(MachineDomTreeNode *N, bool IsHeader = false);
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void HoistRegion(MachineDomTreeNode *N, bool IsHeader = false);
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/// getRegisterClassIDAndCost - For a given MI, register, and the operand
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/// index, return the ID and cost of its representative register class by
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/// reference.
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void getRegisterClassIDAndCost(const MachineInstr *MI,
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unsigned Reg, unsigned OpIdx,
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unsigned &RCId, unsigned &RCCost) const;
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/// InitRegPressure - Find all virtual register references that are liveout
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/// InitRegPressure - Find all virtual register references that are liveout
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/// of the preheader to initialize the starting "register pressure". Note
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/// of the preheader to initialize the starting "register pressure". Note
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/// this does not count live through (livein but not used) registers.
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/// this does not count live through (livein but not used) registers.
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@ -596,6 +603,23 @@ static bool isOperandKill(const MachineOperand &MO, MachineRegisterInfo *MRI) {
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return MO.isKill() || MRI->hasOneNonDBGUse(MO.getReg());
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return MO.isKill() || MRI->hasOneNonDBGUse(MO.getReg());
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}
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}
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/// getRegisterClassIDAndCost - For a given MI, register, and the operand
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/// index, return the ID and cost of its representative register class.
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void
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MachineLICM::getRegisterClassIDAndCost(const MachineInstr *MI,
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unsigned Reg, unsigned OpIdx,
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unsigned &RCId, unsigned &RCCost) const {
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const TargetRegisterClass *RC = MRI->getRegClass(Reg);
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EVT VT = *RC->vt_begin();
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if (VT == MVT::untyped) {
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RCId = RC->getID();
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RCCost = 1;
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} else {
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RCId = TLI->getRepRegClassFor(VT)->getID();
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RCCost = TLI->getRepRegClassCostFor(VT);
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}
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}
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/// InitRegPressure - Find all virtual register references that are liveout of
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/// InitRegPressure - Find all virtual register references that are liveout of
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/// the preheader to initialize the starting "register pressure". Note this
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/// the preheader to initialize the starting "register pressure". Note this
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/// does not count live through (livein but not used) registers.
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/// does not count live through (livein but not used) registers.
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@ -625,18 +649,17 @@ void MachineLICM::InitRegPressure(MachineBasicBlock *BB) {
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continue;
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continue;
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bool isNew = RegSeen.insert(Reg);
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bool isNew = RegSeen.insert(Reg);
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const TargetRegisterClass *RC = MRI->getRegClass(Reg);
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unsigned RCId, RCCost;
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EVT VT = *RC->vt_begin();
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getRegisterClassIDAndCost(MI, Reg, i, RCId, RCCost);
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unsigned RCId = TLI->getRepRegClassFor(VT)->getID();
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if (MO.isDef())
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if (MO.isDef())
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RegPressure[RCId] += TLI->getRepRegClassCostFor(VT);
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RegPressure[RCId] += RCCost;
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else {
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else {
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bool isKill = isOperandKill(MO, MRI);
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bool isKill = isOperandKill(MO, MRI);
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if (isNew && !isKill)
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if (isNew && !isKill)
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// Haven't seen this, it must be a livein.
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// Haven't seen this, it must be a livein.
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RegPressure[RCId] += TLI->getRepRegClassCostFor(VT);
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RegPressure[RCId] += RCCost;
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else if (!isNew && isKill)
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else if (!isNew && isKill)
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RegPressure[RCId] -= TLI->getRepRegClassCostFor(VT);
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RegPressure[RCId] -= RCCost;
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}
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}
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}
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}
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}
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}
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@ -661,11 +684,8 @@ void MachineLICM::UpdateRegPressure(const MachineInstr *MI) {
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if (MO.isDef())
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if (MO.isDef())
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Defs.push_back(Reg);
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Defs.push_back(Reg);
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else if (!isNew && isOperandKill(MO, MRI)) {
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else if (!isNew && isOperandKill(MO, MRI)) {
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const TargetRegisterClass *RC = MRI->getRegClass(Reg);
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unsigned RCId, RCCost;
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EVT VT = *RC->vt_begin();
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getRegisterClassIDAndCost(MI, Reg, i, RCId, RCCost);
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unsigned RCId = TLI->getRepRegClassFor(VT)->getID();
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unsigned RCCost = TLI->getRepRegClassCostFor(VT);
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if (RCCost > RegPressure[RCId])
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if (RCCost > RegPressure[RCId])
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RegPressure[RCId] = 0;
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RegPressure[RCId] = 0;
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else
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else
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@ -673,13 +693,13 @@ void MachineLICM::UpdateRegPressure(const MachineInstr *MI) {
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}
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}
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}
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}
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unsigned Idx = 0;
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while (!Defs.empty()) {
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while (!Defs.empty()) {
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unsigned Reg = Defs.pop_back_val();
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unsigned Reg = Defs.pop_back_val();
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const TargetRegisterClass *RC = MRI->getRegClass(Reg);
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unsigned RCId, RCCost;
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EVT VT = *RC->vt_begin();
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getRegisterClassIDAndCost(MI, Reg, Idx, RCId, RCCost);
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unsigned RCId = TLI->getRepRegClassFor(VT)->getID();
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unsigned RCCost = TLI->getRepRegClassCostFor(VT);
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RegPressure[RCId] += RCCost;
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RegPressure[RCId] += RCCost;
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++Idx;
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}
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}
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}
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}
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@ -879,10 +899,8 @@ void MachineLICM::UpdateBackTraceRegPressure(const MachineInstr *MI) {
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if (!TargetRegisterInfo::isVirtualRegister(Reg))
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if (!TargetRegisterInfo::isVirtualRegister(Reg))
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continue;
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continue;
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const TargetRegisterClass *RC = MRI->getRegClass(Reg);
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unsigned RCId, RCCost;
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EVT VT = *RC->vt_begin();
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getRegisterClassIDAndCost(MI, Reg, i, RCId, RCCost);
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unsigned RCId = TLI->getRepRegClassFor(VT)->getID();
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unsigned RCCost = TLI->getRepRegClassCostFor(VT);
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if (MO.isDef()) {
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if (MO.isDef()) {
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DenseMap<unsigned, int>::iterator CI = Cost.find(RCId);
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DenseMap<unsigned, int>::iterator CI = Cost.find(RCId);
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if (CI != Cost.end())
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if (CI != Cost.end())
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@ -941,16 +959,15 @@ bool MachineLICM::IsProfitableToHoist(MachineInstr &MI) {
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unsigned Reg = MO.getReg();
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unsigned Reg = MO.getReg();
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if (!TargetRegisterInfo::isVirtualRegister(Reg))
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if (!TargetRegisterInfo::isVirtualRegister(Reg))
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continue;
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continue;
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unsigned RCId, RCCost;
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getRegisterClassIDAndCost(&MI, Reg, i, RCId, RCCost);
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if (MO.isDef()) {
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if (MO.isDef()) {
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if (HasHighOperandLatency(MI, i, Reg)) {
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if (HasHighOperandLatency(MI, i, Reg)) {
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++NumHighLatency;
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++NumHighLatency;
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return true;
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return true;
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}
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}
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const TargetRegisterClass *RC = MRI->getRegClass(Reg);
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EVT VT = *RC->vt_begin();
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unsigned RCId = TLI->getRepRegClassFor(VT)->getID();
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unsigned RCCost = TLI->getRepRegClassCostFor(VT);
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DenseMap<unsigned, int>::iterator CI = Cost.find(RCId);
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DenseMap<unsigned, int>::iterator CI = Cost.find(RCId);
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if (CI != Cost.end())
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if (CI != Cost.end())
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CI->second += RCCost;
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CI->second += RCCost;
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@ -960,10 +977,6 @@ bool MachineLICM::IsProfitableToHoist(MachineInstr &MI) {
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// Is a virtual register use is a kill, hoisting it out of the loop
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// Is a virtual register use is a kill, hoisting it out of the loop
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// may actually reduce register pressure or be register pressure
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// may actually reduce register pressure or be register pressure
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// neutral.
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// neutral.
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const TargetRegisterClass *RC = MRI->getRegClass(Reg);
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EVT VT = *RC->vt_begin();
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unsigned RCId = TLI->getRepRegClassFor(VT)->getID();
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unsigned RCCost = TLI->getRepRegClassCostFor(VT);
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DenseMap<unsigned, int>::iterator CI = Cost.find(RCId);
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DenseMap<unsigned, int>::iterator CI = Cost.find(RCId);
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if (CI != Cost.end())
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if (CI != Cost.end())
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CI->second -= RCCost;
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CI->second -= RCCost;
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