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Add AND/OR/XOR
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23232 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -223,8 +223,11 @@ class XForm_base_r3xo_swapped
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class XForm_1<bits<6> opcode, bits<10> xo, dag OL, string asmstr>
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: XForm_base_r3xo<opcode, xo, OL, asmstr>;
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class XForm_6<bits<6> opcode, bits<10> xo, dag OL, string asmstr>
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: XForm_base_r3xo_swapped<opcode, xo, OL, asmstr>;
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class XForm_6<bits<6> opcode, bits<10> xo, dag OL, string asmstr,
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list<dag> pattern>
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: XForm_base_r3xo_swapped<opcode, xo, OL, asmstr> {
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let Pattern = pattern;
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}
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class XForm_8<bits<6> opcode, bits<10> xo, dag OL, string asmstr>
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: XForm_base_r3xo<opcode, xo, OL, asmstr>;
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@ -233,9 +236,11 @@ class XForm_10<bits<6> opcode, bits<10> xo, dag OL, string asmstr>
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: XForm_base_r3xo_swapped<opcode, xo, OL, asmstr> {
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}
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class XForm_11<bits<6> opcode, bits<10> xo, dag OL, string asmstr>
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class XForm_11<bits<6> opcode, bits<10> xo, dag OL, string asmstr,
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list<dag> pattern>
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: XForm_base_r3xo_swapped<opcode, xo, OL, asmstr> {
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let B = 0;
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let Pattern = pattern;
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}
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class XForm_16<bits<6> opcode, bits<10> xo, dag OL, string asmstr>
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@ -14,14 +14,24 @@
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include "PowerPCInstrFormats.td"
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class SDNode<string Opc> {
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string Opcode = Opc;
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}
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def set;
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def mul;
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def udiv;
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def sdiv;
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def sub;
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def add;
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def mulhs;
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def mulhu;
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def and : SDNode<"ISD::AND">;
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def or : SDNode<"ISD::OR">;
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def xor : SDNode<"ISD::XOR">;
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def add : SDNode<"ISD::ADD">;
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def sub : SDNode<"ISD::SUB">;
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def mul : SDNode<"ISD::MUL">;
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def sdiv : SDNode<"ISD::SDIV">;
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def udiv : SDNode<"ISD::UDIV">;
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def mulhs : SDNode<"ISD::MULHS">;
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def mulhu : SDNode<"ISD::MULHU">;
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def sext_inreg : SDNode<"ISD::SIGN_EXTEND_INREG">;
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def ctlz : SDNode<"ISD::CTLZ">;
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class isPPC64 { bit PPC64 = 1; }
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class isVMX { bit VMX = 1; }
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@ -240,37 +250,53 @@ def LDX : XForm_1<31, 21, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
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"ldx $dst, $base, $index">, isPPC64;
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}
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def AND : XForm_6<31, 28, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
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"and $rA, $rS, $rB">;
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"and $rA, $rS, $rB",
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[(set GPRC:$rT, (and GPRC:$rA, GPRC:$rB))]>;
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def ANDo : XForm_6<31, 28, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
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"and. $rA, $rS, $rB">, isDOT;
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"and. $rA, $rS, $rB",
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[]>, isDOT;
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def ANDC : XForm_6<31, 60, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
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"andc $rA, $rS, $rB">;
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"andc $rA, $rS, $rB",
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[]>;
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def EQV : XForm_6<31, 284, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
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"eqv $rA, $rS, $rB">;
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"eqv $rA, $rS, $rB",
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[]>;
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def NAND : XForm_6<31, 476, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
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"nand $rA, $rS, $rB">;
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"nand $rA, $rS, $rB",
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[]>;
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def NOR : XForm_6<31, 124, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
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"nor $rA, $rS, $rB">;
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"nor $rA, $rS, $rB",
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[]>;
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def OR : XForm_6<31, 444, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
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"or $rA, $rS, $rB">;
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"or $rA, $rS, $rB",
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[(set GPRC:$rT, (or GPRC:$rA, GPRC:$rB))]>;
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def ORo : XForm_6<31, 444, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
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"or. $rA, $rS, $rB">, isDOT;
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"or. $rA, $rS, $rB",
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[]>, isDOT;
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def ORC : XForm_6<31, 412, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
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"orc $rA, $rS, $rB">;
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"orc $rA, $rS, $rB",
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[]>;
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def SLD : XForm_6<31, 27, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
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"sld $rA, $rS, $rB">, isPPC64;
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"sld $rA, $rS, $rB",
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[]>, isPPC64;
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def SLW : XForm_6<31, 24, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
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"slw $rA, $rS, $rB">;
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"slw $rA, $rS, $rB",
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[]>;
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def SRD : XForm_6<31, 539, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
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"srd $rA, $rS, $rB">, isPPC64;
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"srd $rA, $rS, $rB",
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[]>, isPPC64;
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def SRW : XForm_6<31, 536, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
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"srw $rA, $rS, $rB">;
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"srw $rA, $rS, $rB",
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[]>;
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def SRAD : XForm_6<31, 794, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
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"srad $rA, $rS, $rB">, isPPC64;
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"srad $rA, $rS, $rB",
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[]>, isPPC64;
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def SRAW : XForm_6<31, 792, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
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"sraw $rA, $rS, $rB">;
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"sraw $rA, $rS, $rB",
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[]>;
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def XOR : XForm_6<31, 316, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
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"xor $rA, $rS, $rB">;
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"xor $rA, $rS, $rB",
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[(set GPRC:$rT, (xor GPRC:$rA, GPRC:$rB))]>;
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let isStore = 1 in {
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def STBX : XForm_8<31, 215, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
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"stbx $rS, $rA, $rB">;
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@ -288,13 +314,17 @@ def STDUX : XForm_8<31, 181, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
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def SRAWI : XForm_10<31, 824, (ops GPRC:$rA, GPRC:$rS, u5imm:$SH),
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"srawi $rA, $rS, $SH">;
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def CNTLZW : XForm_11<31, 26, (ops GPRC:$rA, GPRC:$rS),
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"cntlzw $rA, $rS">;
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"cntlzw $rA, $rS",
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[(set GPRC:$rA, (ctlz GPRC:$rS))]>;
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def EXTSB : XForm_11<31, 954, (ops GPRC:$rA, GPRC:$rS),
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"extsb $rA, $rS">;
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"extsb $rA, $rS",
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[(set GPRC:$rA, (sext_inreg GPRC:$rS, i8))]>;
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def EXTSH : XForm_11<31, 922, (ops GPRC:$rA, GPRC:$rS),
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"extsh $rA, $rS">;
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"extsh $rA, $rS",
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[(set GPRC:$rA, (sext_inreg GPRC:$rS, i16))]>;
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def EXTSW : XForm_11<31, 986, (ops GPRC:$rA, GPRC:$rS),
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"extsw $rA, $rS">, isPPC64;
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"extsw $rA, $rS",
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[]>, isPPC64;
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def CMP : XForm_16<31, 0, (ops CRRC:$crD, i1imm:$long, GPRC:$rA, GPRC:$rB),
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"cmp $crD, $long, $rA, $rB">;
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def CMPL : XForm_16<31, 32, (ops CRRC:$crD, i1imm:$long, GPRC:$rA, GPRC:$rB),
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@ -512,4 +542,3 @@ def PowerPCInstrInfo : InstrInfo {
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let isLittleEndianEncoding = 1;
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}
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