From 615a279f81e08e9c63fd5e411b33d39bfe593314 Mon Sep 17 00:00:00 2001
From: Akira Hatanaka <ahatanaka@mips.com>
Date: Tue, 29 Oct 2013 19:29:03 +0000
Subject: [PATCH] [mips] Align the stack to 16-bytes for mfp64.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193641 91177308-0d34-0410-b5e6-96231b3b80d8
---
 lib/Target/Mips/Mips.td               |  4 +++-
 lib/Target/Mips/Mips16FrameLowering.h |  2 +-
 lib/Target/Mips/MipsSEFrameLowering.h |  2 +-
 lib/Target/Mips/MipsSubtarget.cpp     |  2 +-
 lib/Target/Mips/MipsSubtarget.h       |  5 +++++
 test/CodeGen/Mips/stack-alignment.ll  | 14 ++++++++++++++
 6 files changed, 25 insertions(+), 4 deletions(-)
 create mode 100644 test/CodeGen/Mips/stack-alignment.ll

diff --git a/lib/Target/Mips/Mips.td b/lib/Target/Mips/Mips.td
index b8e3f39256d..0581d84a054 100644
--- a/lib/Target/Mips/Mips.td
+++ b/lib/Target/Mips/Mips.td
@@ -30,10 +30,12 @@ def MipsInstrInfo : InstrInfo;
 // Mips Subtarget features                                                    //
 //===----------------------------------------------------------------------===//
 
+def StackAlign16 : SubtargetFeature<"stackalign16", "StackAlignment", "16",
+                                    "Set stack alignment to 16-bytes.">;
 def FeatureGP64Bit     : SubtargetFeature<"gp64", "IsGP64bit", "true",
                                 "General Purpose Registers are 64-bit wide.">;
 def FeatureFP64Bit     : SubtargetFeature<"fp64", "IsFP64bit", "true",
-                                "Support 64-bit FP registers.">;
+                                "Support 64-bit FP registers.", [StackAlign16]>;
 def FeatureSingleFloat : SubtargetFeature<"single-float", "IsSingleFloat",
                                 "true", "Only supports single precision float">;
 def FeatureO32         : SubtargetFeature<"o32", "MipsABI", "O32",
diff --git a/lib/Target/Mips/Mips16FrameLowering.h b/lib/Target/Mips/Mips16FrameLowering.h
index 54fdb787146..8ce2ceda7c7 100644
--- a/lib/Target/Mips/Mips16FrameLowering.h
+++ b/lib/Target/Mips/Mips16FrameLowering.h
@@ -20,7 +20,7 @@ namespace llvm {
 class Mips16FrameLowering : public MipsFrameLowering {
 public:
   explicit Mips16FrameLowering(const MipsSubtarget &STI)
-    : MipsFrameLowering(STI, 8) {}
+    : MipsFrameLowering(STI, STI.stackAlignment()) {}
 
   /// emitProlog/emitEpilog - These methods insert prolog and epilog code into
   /// the function.
diff --git a/lib/Target/Mips/MipsSEFrameLowering.h b/lib/Target/Mips/MipsSEFrameLowering.h
index 193a66cc65a..8fa9e469887 100644
--- a/lib/Target/Mips/MipsSEFrameLowering.h
+++ b/lib/Target/Mips/MipsSEFrameLowering.h
@@ -21,7 +21,7 @@ namespace llvm {
 class MipsSEFrameLowering : public MipsFrameLowering {
 public:
   explicit MipsSEFrameLowering(const MipsSubtarget &STI)
-    : MipsFrameLowering(STI, STI.hasMips64() ? 16 : 8) {}
+    : MipsFrameLowering(STI, STI.stackAlignment()) {}
 
   /// emitProlog/emitEpilog - These methods insert prolog and epilog code into
   /// the function.
diff --git a/lib/Target/Mips/MipsSubtarget.cpp b/lib/Target/Mips/MipsSubtarget.cpp
index 0a81072b085..07957ef61be 100644
--- a/lib/Target/Mips/MipsSubtarget.cpp
+++ b/lib/Target/Mips/MipsSubtarget.cpp
@@ -72,7 +72,7 @@ MipsSubtarget::MipsSubtarget(const std::string &TT, const std::string &CPU,
   InMips16Mode(false), InMips16HardFloat(Mips16HardFloat),
   InMicroMipsMode(false), HasDSP(false), HasDSPR2(false),
   AllowMixed16_32(Mixed16_32 | Mips_Os16), Os16(Mips_Os16), HasMSA(false),
-  RM(_RM), OverrideMode(NoOverride), TM(_TM)
+  StackAlignment(8), RM(_RM), OverrideMode(NoOverride), TM(_TM)
 {
   std::string CPUName = CPU;
   if (CPUName.empty())
diff --git a/lib/Target/Mips/MipsSubtarget.h b/lib/Target/Mips/MipsSubtarget.h
index 30100656fe0..378fc00f452 100644
--- a/lib/Target/Mips/MipsSubtarget.h
+++ b/lib/Target/Mips/MipsSubtarget.h
@@ -116,6 +116,8 @@ protected:
   // HasMSA -- supports MSA ASE.
   bool HasMSA;
 
+  unsigned StackAlignment;
+
   InstrItineraryData InstrItins;
 
   // The instance to the register info section object
@@ -216,6 +218,9 @@ public:
 // really use them if in addition we are in mips16 mode
 //
 static bool useConstantIslands();
+
+  unsigned stackAlignment() const { return StackAlignment; }
+
   // Grab MipsRegInfo object
   const MipsReginfo &getMReginfo() const { return MRI; }
 
diff --git a/test/CodeGen/Mips/stack-alignment.ll b/test/CodeGen/Mips/stack-alignment.ll
new file mode 100644
index 00000000000..403a10625f4
--- /dev/null
+++ b/test/CodeGen/Mips/stack-alignment.ll
@@ -0,0 +1,14 @@
+; RUN: llc -march=mipsel < %s | FileCheck %s -check-prefix=32
+; RUN: llc -march=mipsel -mattr=+fp64 < %s | FileCheck %s -check-prefix=32-FP64
+; RUN: llc -march=mips64el -mcpu=mips64 < %s | FileCheck %s -check-prefix=64
+
+; 32:      addiu  $sp, $sp, -8
+; 32-FP64: addiu  $sp, $sp, -16
+; 64:      addiu  $sp, $sp, -16
+
+define i32 @foo1() #0 {
+entry:
+  ret i32 14
+}
+
+attributes #0 = { "no-frame-pointer-elim"="true" }