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andd subcc instructions which is used to create the 'cmp' pseudo instruction

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12744 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner
2004-04-07 05:04:01 +00:00
parent 0d538bbec2
commit 6179047661
2 changed files with 6 additions and 2 deletions
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2
lib/Target/Sparc/SparcInstrInfo.td
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@@ -95,6 +95,7 @@ def ADDrr : F3_1<2, 0b000000, "add">;
// Section B.15 - Subtract Instructions, p. 110 // Section B.15 - Subtract Instructions, p. 110
def SUBrr : F3_1<2, 0b000100, "sub">; def SUBrr : F3_1<2, 0b000100, "sub">;
def SUBCCrr : F3_1<2, 0b010100, "subcc">;
// Section B.18 - Multiply Instructions, p. 113 // Section B.18 - Multiply Instructions, p. 113
def UMULrr : F3_1<2, 0b001010, "umul">; def UMULrr : F3_1<2, 0b001010, "umul">;
@@ -133,3 +134,4 @@ def JMPLri : F3_2<2, 0b111000, "jmpl">; // jmpl [rs1+imm], rd
// Section B.29 - Write State Register Instructions // Section B.29 - Write State Register Instructions
def WRrr : F3_1<2, 0b110000, "wr">; // wr rs1, rs2, rd def WRrr : F3_1<2, 0b110000, "wr">; // wr rs1, rs2, rd
def WRri : F3_2<2, 0b110000, "wr">; // wr rs1, imm, rd def WRri : F3_2<2, 0b110000, "wr">; // wr rs1, imm, rd

2
lib/Target/SparcV8/SparcV8InstrInfo.td
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@@ -95,6 +95,7 @@ def ADDrr : F3_1<2, 0b000000, "add">;
// Section B.15 - Subtract Instructions, p. 110 // Section B.15 - Subtract Instructions, p. 110
def SUBrr : F3_1<2, 0b000100, "sub">; def SUBrr : F3_1<2, 0b000100, "sub">;
def SUBCCrr : F3_1<2, 0b010100, "subcc">;
// Section B.18 - Multiply Instructions, p. 113 // Section B.18 - Multiply Instructions, p. 113
def UMULrr : F3_1<2, 0b001010, "umul">; def UMULrr : F3_1<2, 0b001010, "umul">;
@@ -133,3 +134,4 @@ def JMPLri : F3_2<2, 0b111000, "jmpl">; // jmpl [rs1+imm], rd
// Section B.29 - Write State Register Instructions // Section B.29 - Write State Register Instructions
def WRrr : F3_1<2, 0b110000, "wr">; // wr rs1, rs2, rd def WRrr : F3_1<2, 0b110000, "wr">; // wr rs1, rs2, rd
def WRri : F3_2<2, 0b110000, "wr">; // wr rs1, imm, rd def WRri : F3_2<2, 0b110000, "wr">; // wr rs1, imm, rd