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Remove underscores from TBM instruction names for consistency with other instruction naming.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192040 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -1953,10 +1953,10 @@ let hasSideEffects = 0 in {
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multiclass tbm_binary_intr<bits<8> opc, string OpcodeStr,
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Format FormReg, Format FormMem> {
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defm _32 : tbm_binary_rm<opc, FormReg, FormMem, GR32, OpcodeStr, i32mem,
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loadi32>;
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defm _64 : tbm_binary_rm<opc, FormReg, FormMem, GR64, OpcodeStr, i64mem,
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loadi64>, VEX_W;
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defm NAME#32 : tbm_binary_rm<opc, FormReg, FormMem, GR32, OpcodeStr, i32mem,
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loadi32>;
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defm NAME#64 : tbm_binary_rm<opc, FormReg, FormMem, GR64, OpcodeStr, i64mem,
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loadi64>, VEX_W;
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}
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defm BLCFILL : tbm_binary_intr<0x01, "blcfill", MRM1r, MRM1m>;
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@ -1986,55 +1986,55 @@ let Predicates = [HasTBM] in {
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// FIXME: patterns for the load versions are not implemented
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def : Pat<(and GR32:$src, (add GR32:$src, 1)),
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(BLCFILL_32rr GR32:$src)>;
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(BLCFILL32rr GR32:$src)>;
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def : Pat<(and GR64:$src, (add GR64:$src, 1)),
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(BLCFILL_64rr GR64:$src)>;
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(BLCFILL64rr GR64:$src)>;
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def : Pat<(or GR32:$src, (not (add GR32:$src, 1))),
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(BLCI_32rr GR32:$src)>;
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(BLCI32rr GR32:$src)>;
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def : Pat<(or GR64:$src, (not (add GR64:$src, 1))),
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(BLCI_64rr GR64:$src)>;
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(BLCI64rr GR64:$src)>;
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// Extra patterns because opt can optimize the above patterns to this.
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def : Pat<(or GR32:$src, (sub -2, GR32:$src)),
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(BLCI_32rr GR32:$src)>;
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(BLCI32rr GR32:$src)>;
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def : Pat<(or GR64:$src, (sub -2, GR64:$src)),
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(BLCI_64rr GR64:$src)>;
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(BLCI64rr GR64:$src)>;
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def : Pat<(and (not GR32:$src), (add GR32:$src, 1)),
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(BLCIC_32rr GR32:$src)>;
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(BLCIC32rr GR32:$src)>;
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def : Pat<(and (not GR64:$src), (add GR64:$src, 1)),
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(BLCIC_64rr GR64:$src)>;
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(BLCIC64rr GR64:$src)>;
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def : Pat<(xor GR32:$src, (add GR32:$src, 1)),
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(BLCMSK_32rr GR32:$src)>;
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(BLCMSK32rr GR32:$src)>;
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def : Pat<(xor GR64:$src, (add GR64:$src, 1)),
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(BLCMSK_64rr GR64:$src)>;
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(BLCMSK64rr GR64:$src)>;
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def : Pat<(or GR32:$src, (add GR32:$src, 1)),
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(BLCS_32rr GR32:$src)>;
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(BLCS32rr GR32:$src)>;
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def : Pat<(or GR64:$src, (add GR64:$src, 1)),
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(BLCS_64rr GR64:$src)>;
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(BLCS64rr GR64:$src)>;
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def : Pat<(or GR32:$src, (add GR32:$src, -1)),
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(BLSFILL_32rr GR32:$src)>;
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(BLSFILL32rr GR32:$src)>;
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def : Pat<(or GR64:$src, (add GR64:$src, -1)),
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(BLSFILL_64rr GR64:$src)>;
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(BLSFILL64rr GR64:$src)>;
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def : Pat<(or (not GR32:$src), (add GR32:$src, -1)),
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(BLSIC_32rr GR32:$src)>;
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(BLSIC32rr GR32:$src)>;
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def : Pat<(or (not GR64:$src), (add GR64:$src, -1)),
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(BLSIC_64rr GR64:$src)>;
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(BLSIC64rr GR64:$src)>;
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def : Pat<(or (not GR32:$src), (add GR32:$src, 1)),
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(T1MSKC_32rr GR32:$src)>;
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(T1MSKC32rr GR32:$src)>;
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def : Pat<(or (not GR64:$src), (add GR64:$src, 1)),
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(T1MSKC_64rr GR64:$src)>;
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(T1MSKC64rr GR64:$src)>;
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def : Pat<(and (not GR32:$src), (add GR32:$src, -1)),
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(TZMSK_32rr GR32:$src)>;
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(TZMSK32rr GR32:$src)>;
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def : Pat<(and (not GR64:$src), (add GR64:$src, -1)),
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(TZMSK_64rr GR64:$src)>;
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(TZMSK64rr GR64:$src)>;
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} // HasTBM
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//===----------------------------------------------------------------------===//
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