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Remove the useless pseudo instructions VDUPfdf and VDUPfqf, replacing them with patterns to match VDUPLN.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199675 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
James Molloy 2014-01-20 17:14:48 +00:00
parent 95dd2f4e8d
commit 61a7bb039a
3 changed files with 39 additions and 32 deletions
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27
lib/Target/ARM/ARMExpandPseudoInsts.cpp
View File

@ -1079,33 +1079,6 @@ bool ARMExpandPseudo::ExpandMI(MachineBasicBlock &MBB,
MI.eraseFromParent();
return true;
}
case ARM::VDUPfqf:
case ARM::VDUPfdf:{
unsigned NewOpc = Opcode == ARM::VDUPfqf ? ARM::VDUPLN32q :
ARM::VDUPLN32d;
MachineInstrBuilder MIB =
BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc));
unsigned OpIdx = 0;
unsigned SrcReg = MI.getOperand(1).getReg();
unsigned Lane = TRI->getEncodingValue(SrcReg) & 1;
unsigned DReg = TRI->getMatchingSuperReg(SrcReg,
Lane & 1 ? ARM::ssub_1 : ARM::ssub_0,
&ARM::DPR_VFP2RegClass);
// The lane is [0,1] for the containing DReg superregister.
// Copy the dst/src register operands.
MIB.addOperand(MI.getOperand(OpIdx++));
MIB.addReg(DReg);
++OpIdx;
// Add the lane select operand.
MIB.addImm(Lane);
// Add the predicate operands.
MIB.addOperand(MI.getOperand(OpIdx++));
MIB.addOperand(MI.getOperand(OpIdx++));
TransferImpOps(MI, MIB, MIB);
MI.eraseFromParent();
return true;
}
case ARM::VLD2q8Pseudo:
case ARM::VLD2q16Pseudo:

10
lib/Target/ARM/ARMInstrNEON.td
View File

@ -5490,10 +5490,12 @@ def : Pat<(v4f32 (NEONvduplane (v4f32 QPR:$src), imm:$lane)),
(DSubReg_i32_reg imm:$lane))),
(SubReg_i32_lane imm:$lane)))>;
def VDUPfdf : PseudoNeonI<(outs DPR:$dst), (ins SPR:$src), IIC_VMOVD, "",
[(set DPR:$dst, (v2f32 (NEONvdup (f32 SPR:$src))))]>;
def VDUPfqf : PseudoNeonI<(outs QPR:$dst), (ins SPR:$src), IIC_VMOVD, "",
[(set QPR:$dst, (v4f32 (NEONvdup (f32 SPR:$src))))]>;
def : Pat<(v2f32 (NEONvdup (f32 SPR:$src))),
(v2f32 (VDUPLN32d (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)),
SPR:$src, ssub_0), (i32 0)))>;
def : Pat<(v4f32 (NEONvdup (f32 SPR:$src))),
(v4f32 (VDUPLN32q (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)),
SPR:$src, ssub_0), (i32 0)))>;
// VMOVN : Vector Narrowing Move
defm VMOVN : N2VN_HSD<0b11,0b11,0b10,0b00100,0,0, IIC_VMOVN,

34
test/CodeGen/ARM/vdup.ll
View File

@ -1,4 +1,4 @@
; RUN: llc < %s -march=arm -float-abi=soft -mattr=+neon | FileCheck %s
; RUN: llc < %s -march=arm -float-abi=soft -mattr=+neon -verify-machineinstrs | FileCheck %s
define <8 x i8> @v_dup8(i8 %A) nounwind {
;CHECK-LABEL: v_dup8:
@ -331,3 +331,35 @@ define <8 x i8> @check_i8(<16 x i8> %v) nounwind {
%2 = insertelement <8 x i8> %1, i8 %x, i32 1
ret <8 x i8> %2
}
; Check that an SPR splat produces a vdup.
define <2 x float> @check_spr_splat2(<2 x float> %p, i16 %q) {
;CHECK-LABEL: check_spr_splat2:
;CHECK: vdup.32 d
%conv = sitofp i16 %q to float
%splat.splatinsert = insertelement <2 x float> undef, float %conv, i32 0
%splat.splat = shufflevector <2 x float> %splat.splatinsert, <2 x float> undef, <2 x i32> zeroinitializer
%sub = fsub <2 x float> %splat.splat, %p
ret <2 x float> %sub
}
define <4 x float> @check_spr_splat4(<4 x float> %p, i16 %q) {
;CHECK-LABEL: check_spr_splat4:
;CHECK: vdup.32 q
%conv = sitofp i16 %q to float
%splat.splatinsert = insertelement <4 x float> undef, float %conv, i32 0
%splat.splat = shufflevector <4 x float> %splat.splatinsert, <4 x float> undef, <4 x i32> zeroinitializer
%sub = fsub <4 x float> %splat.splat, %p
ret <4 x float> %sub
}
define <4 x float> @check_spr_splat4_lane1(<4 x float> %p, i16 %q) {
;CHECK-LABEL: check_spr_splat4_lane1:
;CHECK: vdup.32 q{{.*}}, d{{.*}}[1]
%conv = sitofp i16 %q to float
%splat.splatinsert = insertelement <4 x float> undef, float %conv, i32 1
%splat.splat = shufflevector <4 x float> %splat.splatinsert, <4 x float> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
%sub = fsub <4 x float> %splat.splat, %p
ret <4 x float> %sub
}