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https://github.com/c64scene-ar/llvm-6502.git
synced 2024-09-14 04:57:33 +00:00
Remove the useless pseudo instructions VDUPfdf and VDUPfqf, replacing them with patterns to match VDUPLN.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199675 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -1079,33 +1079,6 @@ bool ARMExpandPseudo::ExpandMI(MachineBasicBlock &MBB,
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MI.eraseFromParent();
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MI.eraseFromParent();
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return true;
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return true;
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}
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}
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case ARM::VDUPfqf:
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case ARM::VDUPfdf:{
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unsigned NewOpc = Opcode == ARM::VDUPfqf ? ARM::VDUPLN32q :
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ARM::VDUPLN32d;
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MachineInstrBuilder MIB =
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BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc));
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unsigned OpIdx = 0;
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unsigned SrcReg = MI.getOperand(1).getReg();
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unsigned Lane = TRI->getEncodingValue(SrcReg) & 1;
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unsigned DReg = TRI->getMatchingSuperReg(SrcReg,
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Lane & 1 ? ARM::ssub_1 : ARM::ssub_0,
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&ARM::DPR_VFP2RegClass);
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// The lane is [0,1] for the containing DReg superregister.
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// Copy the dst/src register operands.
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MIB.addOperand(MI.getOperand(OpIdx++));
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MIB.addReg(DReg);
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++OpIdx;
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// Add the lane select operand.
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MIB.addImm(Lane);
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// Add the predicate operands.
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MIB.addOperand(MI.getOperand(OpIdx++));
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MIB.addOperand(MI.getOperand(OpIdx++));
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TransferImpOps(MI, MIB, MIB);
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MI.eraseFromParent();
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return true;
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}
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case ARM::VLD2q8Pseudo:
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case ARM::VLD2q8Pseudo:
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case ARM::VLD2q16Pseudo:
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case ARM::VLD2q16Pseudo:
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@ -5490,10 +5490,12 @@ def : Pat<(v4f32 (NEONvduplane (v4f32 QPR:$src), imm:$lane)),
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(DSubReg_i32_reg imm:$lane))),
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(DSubReg_i32_reg imm:$lane))),
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(SubReg_i32_lane imm:$lane)))>;
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(SubReg_i32_lane imm:$lane)))>;
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def VDUPfdf : PseudoNeonI<(outs DPR:$dst), (ins SPR:$src), IIC_VMOVD, "",
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def : Pat<(v2f32 (NEONvdup (f32 SPR:$src))),
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[(set DPR:$dst, (v2f32 (NEONvdup (f32 SPR:$src))))]>;
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(v2f32 (VDUPLN32d (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)),
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def VDUPfqf : PseudoNeonI<(outs QPR:$dst), (ins SPR:$src), IIC_VMOVD, "",
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SPR:$src, ssub_0), (i32 0)))>;
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[(set QPR:$dst, (v4f32 (NEONvdup (f32 SPR:$src))))]>;
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def : Pat<(v4f32 (NEONvdup (f32 SPR:$src))),
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(v4f32 (VDUPLN32q (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)),
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SPR:$src, ssub_0), (i32 0)))>;
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// VMOVN : Vector Narrowing Move
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// VMOVN : Vector Narrowing Move
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defm VMOVN : N2VN_HSD<0b11,0b11,0b10,0b00100,0,0, IIC_VMOVN,
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defm VMOVN : N2VN_HSD<0b11,0b11,0b10,0b00100,0,0, IIC_VMOVN,
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@ -1,4 +1,4 @@
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; RUN: llc < %s -march=arm -float-abi=soft -mattr=+neon | FileCheck %s
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; RUN: llc < %s -march=arm -float-abi=soft -mattr=+neon -verify-machineinstrs | FileCheck %s
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define <8 x i8> @v_dup8(i8 %A) nounwind {
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define <8 x i8> @v_dup8(i8 %A) nounwind {
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;CHECK-LABEL: v_dup8:
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;CHECK-LABEL: v_dup8:
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@ -331,3 +331,35 @@ define <8 x i8> @check_i8(<16 x i8> %v) nounwind {
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%2 = insertelement <8 x i8> %1, i8 %x, i32 1
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%2 = insertelement <8 x i8> %1, i8 %x, i32 1
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ret <8 x i8> %2
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ret <8 x i8> %2
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}
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}
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; Check that an SPR splat produces a vdup.
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define <2 x float> @check_spr_splat2(<2 x float> %p, i16 %q) {
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;CHECK-LABEL: check_spr_splat2:
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;CHECK: vdup.32 d
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%conv = sitofp i16 %q to float
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%splat.splatinsert = insertelement <2 x float> undef, float %conv, i32 0
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%splat.splat = shufflevector <2 x float> %splat.splatinsert, <2 x float> undef, <2 x i32> zeroinitializer
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%sub = fsub <2 x float> %splat.splat, %p
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ret <2 x float> %sub
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}
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define <4 x float> @check_spr_splat4(<4 x float> %p, i16 %q) {
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;CHECK-LABEL: check_spr_splat4:
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;CHECK: vdup.32 q
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%conv = sitofp i16 %q to float
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%splat.splatinsert = insertelement <4 x float> undef, float %conv, i32 0
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%splat.splat = shufflevector <4 x float> %splat.splatinsert, <4 x float> undef, <4 x i32> zeroinitializer
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%sub = fsub <4 x float> %splat.splat, %p
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ret <4 x float> %sub
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}
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define <4 x float> @check_spr_splat4_lane1(<4 x float> %p, i16 %q) {
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;CHECK-LABEL: check_spr_splat4_lane1:
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;CHECK: vdup.32 q{{.*}}, d{{.*}}[1]
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%conv = sitofp i16 %q to float
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%splat.splatinsert = insertelement <4 x float> undef, float %conv, i32 1
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%splat.splat = shufflevector <4 x float> %splat.splatinsert, <4 x float> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
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%sub = fsub <4 x float> %splat.splat, %p
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ret <4 x float> %sub
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}
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