diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
index 8d1b1021fe6..c009cfcc516 100644
--- a/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
+++ b/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
@@ -1894,15 +1894,12 @@ unsigned RegReductionPQBase::getNodePriority(const SUnit *SU) const {
     // CopyToReg should be close to its uses to facilitate coalescing and
     // avoid spilling.
     return 0;
-  if (SU->getNode() && SU->getNode()->isMachineOpcode()) {
-    Opc = SU->getNode()->getMachineOpcode();
-    if (Opc == TargetOpcode::EXTRACT_SUBREG ||
-        Opc == TargetOpcode::SUBREG_TO_REG ||
-        Opc == TargetOpcode::INSERT_SUBREG)
-      // EXTRACT_SUBREG, INSERT_SUBREG, and SUBREG_TO_REG nodes should be
-      // close to their uses to facilitate coalescing.
-      return 0;
-  }
+  if (Opc == TargetOpcode::EXTRACT_SUBREG ||
+      Opc == TargetOpcode::SUBREG_TO_REG ||
+      Opc == TargetOpcode::INSERT_SUBREG)
+    // EXTRACT_SUBREG, INSERT_SUBREG, and SUBREG_TO_REG nodes should be
+    // close to their uses to facilitate coalescing.
+    return 0;
   if (SU->NumSuccs == 0 && SU->NumPreds != 0)
     // If SU does not have a register use, i.e. it doesn't produce a value
     // that would be consumed (e.g. store), then it terminates a chain of
@@ -2588,15 +2585,12 @@ static bool canEnableCoalescing(SUnit *SU) {
     // avoid spilling.
     return true;
 
-  if (SU->getNode() && SU->getNode()->isMachineOpcode()) {
-    Opc = SU->getNode()->getMachineOpcode();
-    if (Opc == TargetOpcode::EXTRACT_SUBREG ||
-        Opc == TargetOpcode::SUBREG_TO_REG ||
-        Opc == TargetOpcode::INSERT_SUBREG)
-      // EXTRACT_SUBREG, INSERT_SUBREG, and SUBREG_TO_REG nodes should be
-      // close to their uses to facilitate coalescing.
-      return true;
-  }
+  if (Opc == TargetOpcode::EXTRACT_SUBREG ||
+      Opc == TargetOpcode::SUBREG_TO_REG ||
+      Opc == TargetOpcode::INSERT_SUBREG)
+    // EXTRACT_SUBREG, INSERT_SUBREG, and SUBREG_TO_REG nodes should be
+    // close to their uses to facilitate coalescing.
+    return true;
 
   if (SU->NumPreds == 0 && SU->NumSuccs != 0)
     // If SU does not have a register def, schedule it close to its uses