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Use multiclass to define store instructions with base+immediate offset
addressing mode and immediate stored value. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169408 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jyotsna Verma
parent
a7e29c878c
commit
61b632d9f7
@ -1698,15 +1698,67 @@ def POST_STdri_cdnNotPt_V4 : STInst2PI<(outs IntRegs:$dst),
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Requires<[HasV4T]>;
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// Store byte.
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// memb(Rs+#u6:0)=#S8
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let AddedComplexity = 10, isPredicable = 1 in
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def STrib_imm_V4 : STInst<(outs),
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(ins IntRegs:$src1, u6_0Imm:$src2, s8Imm:$src3),
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"memb($src1+#$src2) = #$src3",
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[(truncstorei8 s8ImmPred:$src3, (add (i32 IntRegs:$src1),
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u6_0ImmPred:$src2))]>,
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// multiclass for store instructions with base + immediate offset
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// addressing mode and immediate stored value.
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multiclass ST_Imm_Pbase<string mnemonic, Operand OffsetOp, bit isNot,
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bit isPredNew> {
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let PNewValue = #!if(isPredNew, "new", "") in
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def #NAME# : STInst2<(outs),
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(ins PredRegs:$src1, IntRegs:$src2, OffsetOp:$src3, s6Ext:$src4),
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#!if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
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") ")#mnemonic#"($src2+#$src3) = #$src4",
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[]>,
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Requires<[HasV4T]>;
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}
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multiclass ST_Imm_Pred<string mnemonic, Operand OffsetOp, bit PredNot> {
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let PredSense = #!if(PredNot, "false", "true") in {
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defm _c#NAME# : ST_Imm_Pbase<mnemonic, OffsetOp, PredNot, 0>;
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// Predicate new
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defm _cdn#NAME# : ST_Imm_Pbase<mnemonic, OffsetOp, PredNot, 1>;
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}
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}
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let isExtendable = 1, isExtentSigned = 1, neverHasSideEffects = 1 in
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multiclass ST_Imm<string mnemonic, string CextOp, Operand OffsetOp> {
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let CextOpcode = CextOp, BaseOpcode = CextOp#_imm in {
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let opExtendable = 2, opExtentBits = 8, isPredicable = 1 in
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def #NAME#_V4 : STInst2<(outs),
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(ins IntRegs:$src1, OffsetOp:$src2, s8Ext:$src3),
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#mnemonic#"($src1+#$src2) = #$src3",
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[]>,
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Requires<[HasV4T]>;
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let opExtendable = 3, opExtentBits = 6, isPredicated = 1 in {
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defm Pt_V4 : ST_Imm_Pred<mnemonic, OffsetOp, 0>;
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defm NotPt_V4 : ST_Imm_Pred<mnemonic, OffsetOp, 1 >;
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}
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}
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}
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let addrMode = BaseImmOffset, InputType = "imm",
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validSubTargets = HasV4SubT in {
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defm STrib_imm : ST_Imm<"memb", "STrib", u6_0Imm>, ImmRegRel;
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defm STrih_imm : ST_Imm<"memh", "STrih", u6_1Imm>, ImmRegRel;
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defm STriw_imm : ST_Imm<"memw", "STriw", u6_2Imm>, ImmRegRel;
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}
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let Predicates = [HasV4T], AddedComplexity = 10 in {
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def: Pat<(truncstorei8 s8ExtPred:$src3, (add IntRegs:$src1, u6_0ImmPred:$src2)),
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(STrib_imm_V4 IntRegs:$src1, u6_0ImmPred:$src2, s8ExtPred:$src3)>;
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def: Pat<(truncstorei16 s8ExtPred:$src3, (add IntRegs:$src1,
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u6_1ImmPred:$src2)),
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(STrih_imm_V4 IntRegs:$src1, u6_1ImmPred:$src2, s8ExtPred:$src3)>;
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def: Pat<(store s8ExtPred:$src3, (add IntRegs:$src1, u6_2ImmPred:$src2)),
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(STriw_imm_V4 IntRegs:$src1, u6_2ImmPred:$src2, s8ExtPred:$src3)>;
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}
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let AddedComplexity = 6 in
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def : Pat <(truncstorei8 s8ExtPred:$src2, (i32 IntRegs:$src1)),
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(STrib_imm_V4 IntRegs:$src1, 0, s8ExtPred:$src2)>,
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Requires<[HasV4T]>;
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// memb(Ru<<#u2+#U6)=Rt
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let AddedComplexity = 10 in
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@ -1727,43 +1779,6 @@ def STrib_shl_V4 : STInst<(outs),
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// Store byte conditionally.
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// if ([!]Pv[.new]) memb(#u6)=Rt
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// if ([!]Pv[.new]) memb(Rs+#u6:0)=#S6
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// if (Pv) memb(Rs+#u6:0)=#S6
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let neverHasSideEffects = 1,
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isPredicated = 1 in
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def STrib_imm_cPt_V4 : STInst2<(outs),
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(ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3, s6Imm:$src4),
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"if ($src1) memb($src2+#$src3) = #$src4",
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[]>,
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Requires<[HasV4T]>;
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// if (Pv.new) memb(Rs+#u6:0)=#S6
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let neverHasSideEffects = 1,
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isPredicated = 1 in
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def STrib_imm_cdnPt_V4 : STInst2<(outs),
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(ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3, s6Imm:$src4),
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"if ($src1.new) memb($src2+#$src3) = #$src4",
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[]>,
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Requires<[HasV4T]>;
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// if (!Pv) memb(Rs+#u6:0)=#S6
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let neverHasSideEffects = 1,
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isPredicated = 1 in
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def STrib_imm_cNotPt_V4 : STInst2<(outs),
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(ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3, s6Imm:$src4),
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"if (!$src1) memb($src2+#$src3) = #$src4",
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[]>,
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Requires<[HasV4T]>;
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// if (!Pv.new) memb(Rs+#u6:0)=#S6
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let neverHasSideEffects = 1,
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isPredicated = 1 in
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def STrib_imm_cdnNotPt_V4 : STInst2<(outs),
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(ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3, s6Imm:$src4),
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"if (!$src1.new) memb($src2+#$src3) = #$src4",
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[]>,
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Requires<[HasV4T]>;
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// if ([!]Pv[.new]) memb(Rx++#s4:0)=Rt
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// if (Pv) memb(Rx++#s4:0)=Rt
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// if (Pv.new) memb(Rx++#s4:0)=Rt
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@ -1790,14 +1805,10 @@ def POST_STbri_cdnNotPt_V4 : STInst2PI<(outs IntRegs:$dst),
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// TODO: needs to be implemented
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// memh(Re=#U6)=Rt.H
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// memh(Rs+#s11:1)=Rt.H
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// memh(Rs+#u6:1)=#S8
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let AddedComplexity = 10, isPredicable = 1 in
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def STrih_imm_V4 : STInst<(outs),
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(ins IntRegs:$src1, u6_1Imm:$src2, s8Imm:$src3),
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"memh($src1+#$src2) = #$src3",
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[(truncstorei16 s8ImmPred:$src3, (add (i32 IntRegs:$src1),
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u6_1ImmPred:$src2))]>,
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Requires<[HasV4T]>;
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let AddedComplexity = 6 in
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def : Pat <(truncstorei16 s8ExtPred:$src2, (i32 IntRegs:$src1)),
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(STrih_imm_V4 IntRegs:$src1, 0, s8ExtPred:$src2)>,
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Requires<[HasV4T]>;
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// memh(Rs+Ru<<#u2)=Rt.H
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// TODO: needs to be implemented.
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@ -1825,42 +1836,6 @@ def STrih_shl_V4 : STInst<(outs),
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// if ([!]Pv[.new]) memh(#u6)=Rt.H
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// if ([!]Pv[.new]) memh(#u6)=Rt
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// if ([!]Pv[.new]) memh(Rs+#u6:1)=#S6
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// if (Pv) memh(Rs+#u6:1)=#S6
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let neverHasSideEffects = 1,
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isPredicated = 1 in
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def STrih_imm_cPt_V4 : STInst2<(outs),
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(ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3, s6Imm:$src4),
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"if ($src1) memh($src2+#$src3) = #$src4",
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[]>,
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Requires<[HasV4T]>;
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// if (Pv.new) memh(Rs+#u6:1)=#S6
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let neverHasSideEffects = 1,
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isPredicated = 1 in
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def STrih_imm_cdnPt_V4 : STInst2<(outs),
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(ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3, s6Imm:$src4),
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"if ($src1.new) memh($src2+#$src3) = #$src4",
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[]>,
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Requires<[HasV4T]>;
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// if (!Pv) memh(Rs+#u6:1)=#S6
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let neverHasSideEffects = 1,
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isPredicated = 1 in
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def STrih_imm_cNotPt_V4 : STInst2<(outs),
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(ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3, s6Imm:$src4),
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"if (!$src1) memh($src2+#$src3) = #$src4",
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[]>,
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Requires<[HasV4T]>;
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// if (!Pv.new) memh(Rs+#u6:1)=#S6
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let neverHasSideEffects = 1,
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isPredicated = 1 in
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def STrih_imm_cdnNotPt_V4 : STInst2<(outs),
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(ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3, s6Imm:$src4),
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"if (!$src1.new) memh($src2+#$src3) = #$src4",
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[]>,
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Requires<[HasV4T]>;
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// if ([!]Pv[.new]) memh(Rs+#u6:1)=Rt.H
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// TODO: needs to be implemented.
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@ -1902,16 +1877,10 @@ def STriw_pred_V4 : STInst2<(outs),
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[]>,
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Requires<[HasV4T]>;
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// memw(Rs+#u6:2)=#S8
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let AddedComplexity = 10, isPredicable = 1 in
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def STriw_imm_V4 : STInst<(outs),
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(ins IntRegs:$src1, u6_2Imm:$src2, s8Imm:$src3),
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"memw($src1+#$src2) = #$src3",
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[(store s8ImmPred:$src3, (add (i32 IntRegs:$src1),
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u6_2ImmPred:$src2))]>,
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Requires<[HasV4T]>;
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let AddedComplexity = 6 in
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def : Pat <(store s8ExtPred:$src2, (i32 IntRegs:$src1)),
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(STriw_imm_V4 IntRegs:$src1, 0, s8ExtPred:$src2)>,
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Requires<[HasV4T]>;
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// memw(Ru<<#u2+#U6)=Rt
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let AddedComplexity = 10 in
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@ -1931,45 +1900,6 @@ def STriw_shl_V4 : STInst<(outs),
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// memw(gp+#u16:2)=Rt
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// Store word conditionally.
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// if ([!]Pv[.new]) memw(Rs+#u6:2)=#S6
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// if (Pv) memw(Rs+#u6:2)=#S6
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let neverHasSideEffects = 1,
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isPredicated = 1 in
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def STriw_imm_cPt_V4 : STInst2<(outs),
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(ins PredRegs:$src1, IntRegs:$src2, u6_2Imm:$src3, s6Imm:$src4),
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"if ($src1) memw($src2+#$src3) = #$src4",
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[]>,
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Requires<[HasV4T]>;
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// if (Pv.new) memw(Rs+#u6:2)=#S6
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let neverHasSideEffects = 1,
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isPredicated = 1 in
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def STriw_imm_cdnPt_V4 : STInst2<(outs),
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(ins PredRegs:$src1, IntRegs:$src2, u6_2Imm:$src3, s6Imm:$src4),
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"if ($src1.new) memw($src2+#$src3) = #$src4",
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[]>,
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Requires<[HasV4T]>;
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// if (!Pv) memw(Rs+#u6:2)=#S6
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let neverHasSideEffects = 1,
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isPredicated = 1 in
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def STriw_imm_cNotPt_V4 : STInst2<(outs),
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(ins PredRegs:$src1, IntRegs:$src2, u6_2Imm:$src3, s6Imm:$src4),
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"if (!$src1) memw($src2+#$src3) = #$src4",
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[]>,
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Requires<[HasV4T]>;
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// if (!Pv.new) memw(Rs+#u6:2)=#S6
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let neverHasSideEffects = 1,
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isPredicated = 1 in
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def STriw_imm_cdnNotPt_V4 : STInst2<(outs),
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(ins PredRegs:$src1, IntRegs:$src2, u6_2Imm:$src3, s6Imm:$src4),
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"if (!$src1.new) memw($src2+#$src3) = #$src4",
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[]>,
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Requires<[HasV4T]>;
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// if ([!]Pv[.new]) memw(Rx++#s4:2)=Rt
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// if (Pv) memw(Rx++#s4:2)=Rt
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// if (Pv.new) memw(Rx++#s4:2)=Rt
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@ -1,6 +1,5 @@
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; RUN: llc -march=hexagon -mcpu=hexagonv4 -disable-hexagon-misched < %s | FileCheck %s
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; CHECK: r[[T0:[0-9]+]] = #7
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; CHECK: memw(r29 + #0) = r[[T0]]
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; CHECK: memw(r29{{ *}}+{{ *}}#0){{ *}}={{ *}}#7
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; CHECK: r5 = #6
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; CHECK: r0 = #1
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; CHECK: r1 = #2
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@ -1,8 +1,8 @@
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; RUN: llc -march=hexagon -mcpu=hexagonv4 < %s | FileCheck %s
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; Check that we generate dual stores in one packet in V4
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; CHECK: memw(r{{[0-9]+}} + #{{[0-9]+}}) = r{{[0-9]+}}
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; CHECK-NEXT: memw(r{{[0-9]+}} + #{{[0-9]+}}) = r{{[0-9]+}}
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; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#{{[0-9]+}}){{ *}}={{ *}}#100000
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; CHECK-NEXT: memw(r{{[0-9]+}}{{ *}}+{{ *}}#{{[0-9]+}}){{ *}}={{ *}}#500000
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; CHECK-NEXT: }
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@Reg = global i32 0, align 4
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