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When Mips16 frames grow large, the immediate field may exceed the maximum
allowed size for the instruction. This code uses RegScavenger to fix this. We sometimes need 2 registers for Mips16 so we must handle things differently than how register scavenger is normally used. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174696 91177308-0d34-0410-b5e6-96231b3b80d8
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Reed Kotler
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d2bcda7706
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@ -19,6 +19,7 @@
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#include "llvm/ADT/StringRef.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/RegisterScavenging.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/TargetRegistry.h"
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@ -306,11 +307,79 @@ void Mips16InstrInfo::adjustStackPtr(unsigned SP, int64_t Amount,
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/// This function generates the sequence of instructions needed to get the
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/// result of adding register REG and immediate IMM.
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unsigned
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Mips16InstrInfo::loadImmediate(int64_t Imm, MachineBasicBlock &MBB,
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Mips16InstrInfo::loadImmediate(unsigned FrameReg,
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int64_t Imm, MachineBasicBlock &MBB,
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MachineBasicBlock::iterator II, DebugLoc DL,
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unsigned *NewImm) const {
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unsigned &NewImm) const {
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//
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// given original instruction is:
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// Instr rx, T[offset] where offset is too big.
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//
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// lo = offset & 0xFFFF
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// hi = ((offset >> 16) + (lo >> 15)) & 0xFFFF;
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//
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// let T = temporary register
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// li T, hi
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// shl T, 16
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// add T, Rx, T
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//
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RegScavenger rs;
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int32_t lo = Imm & 0xFFFF;
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int32_t hi = ((Imm >> 16) + (lo >> 15)) & 0xFFFF;
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NewImm = lo;
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unsigned Reg =0;
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unsigned SpReg = 0;
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rs.enterBasicBlock(&MBB);
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rs.forward(II);
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//
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// we use T0 for the first register, if we need to save something away.
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// we use T1 for the second register, if we need to save something away.
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//
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unsigned FirstRegSaved =0, SecondRegSaved=0;
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unsigned FirstRegSavedTo = 0, SecondRegSavedTo = 0;
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return 0;
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Reg = rs.FindUnusedReg(&Mips::CPU16RegsRegClass);
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if (Reg == 0) {
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FirstRegSaved = Reg = Mips::V0;
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FirstRegSavedTo = Mips::T0;
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copyPhysReg(MBB, II, DL, FirstRegSavedTo, FirstRegSaved, true);
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}
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else
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rs.setUsed(Reg);
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BuildMI(MBB, II, DL, get(Mips::LiRxImmX16), Reg).addImm(hi);
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BuildMI(MBB, II, DL, get(Mips::SllX16), Reg).addReg(Reg).
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addImm(16);
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if (FrameReg == Mips::SP) {
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SpReg = rs.FindUnusedReg(&Mips::CPU16RegsRegClass);
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if (SpReg == 0) {
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if (Reg != Mips::V1) {
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SecondRegSaved = SpReg = Mips::V1;
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SecondRegSavedTo = Mips::T1;
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}
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else {
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SecondRegSaved = SpReg = Mips::V0;
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SecondRegSavedTo = Mips::T0;
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}
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copyPhysReg(MBB, II, DL, SecondRegSavedTo, SecondRegSaved, true);
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}
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else
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rs.setUsed(SpReg);
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copyPhysReg(MBB, II, DL, SpReg, Mips::SP, false);
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BuildMI(MBB, II, DL, get(Mips:: AdduRxRyRz16), Reg).addReg(SpReg)
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.addReg(Reg);
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}
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else
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BuildMI(MBB, II, DL, get(Mips:: AdduRxRyRz16), Reg).addReg(FrameReg)
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.addReg(Reg, RegState::Kill);
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if (FirstRegSaved || SecondRegSaved) {
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II = llvm::next(II);
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if (FirstRegSaved)
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copyPhysReg(MBB, II, DL, FirstRegSaved, FirstRegSavedTo, true);
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if (SecondRegSaved)
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copyPhysReg(MBB, II, DL, SecondRegSaved, SecondRegSavedTo, true);
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}
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return Reg;
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}
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unsigned Mips16InstrInfo::GetAnalyzableBrOpc(unsigned Opc) const {
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@ -77,12 +77,14 @@ public:
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void adjustStackPtr(unsigned SP, int64_t Amount, MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I) const;
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/// Emit a series of instructions to load an immediate. If NewImm is a
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/// non-NULL parameter, the last instruction is not emitted, but instead
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/// its immediate operand is returned in NewImm.
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unsigned loadImmediate(int64_t Imm, MachineBasicBlock &MBB,
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/// Emit a series of instructions to load an immediate.
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// This is to adjust some FrameReg. We return the new register to be used
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// in place of FrameReg and the adjusted immediate field (&NewImm)
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//
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unsigned loadImmediate(unsigned FrameReg,
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int64_t Imm, MachineBasicBlock &MBB,
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MachineBasicBlock::iterator II, DebugLoc DL,
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unsigned *NewImm) const;
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unsigned &NewImm) const;
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private:
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virtual unsigned GetAnalyzableBrOpc(unsigned Opc) const;
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@ -1,3 +1,4 @@
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//===-- Mips16RegisterInfo.cpp - MIPS16 Register Information -== ----------===//
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//
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// The LLVM Compiler Infrastructure
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@ -12,6 +13,7 @@
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//===----------------------------------------------------------------------===//
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#include "Mips16RegisterInfo.h"
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#include "Mips16InstrInfo.h"
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#include "Mips.h"
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#include "Mips16InstrInfo.h"
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#include "MipsAnalyzeImmediate.h"
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@ -23,6 +25,7 @@
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/ValueTypes.h"
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#include "llvm/DebugInfo.h"
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#include "llvm/IR/Constants.h"
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@ -140,6 +143,7 @@ void Mips16RegisterInfo::eliminateFI(MachineBasicBlock::iterator II,
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// by adding the size of the stack:
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// incoming argument, callee-saved register location or local variable.
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int64_t Offset;
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bool IsKill = false;
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Offset = SPOffset + (int64_t)StackSize;
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Offset += MI.getOperand(OpNo + 1).getImm();
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@ -148,9 +152,14 @@ void Mips16RegisterInfo::eliminateFI(MachineBasicBlock::iterator II,
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if (!MI.isDebugValue() && ( ((FrameReg != Mips::SP) && !isInt<16>(Offset)) ||
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((FrameReg == Mips::SP) && !isInt<15>(Offset)) )) {
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llvm_unreachable("frame offset does not fit in instruction");
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MachineBasicBlock &MBB = *MI.getParent();
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DebugLoc DL = II->getDebugLoc();
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unsigned NewImm;
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FrameReg = TII.loadImmediate(FrameReg, Offset, MBB, II, DL, NewImm);
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Offset = SignExtend64<16>(NewImm);
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IsKill = true;
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}
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MI.getOperand(OpNo).ChangeToRegister(FrameReg, false);
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MI.getOperand(OpNo).ChangeToRegister(FrameReg, false, false, IsKill);
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MI.getOperand(OpNo + 1).ChangeToImmediate(Offset);
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61
test/CodeGen/Mips/largefr1.ll
Normal file
61
test/CodeGen/Mips/largefr1.ll
Normal file
@ -0,0 +1,61 @@
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; RUN: llc -march=mipsel -mcpu=mips16 -mips16-hard-float -soft-float -relocation-model=static < %s | FileCheck %s -check-prefix=1
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@i = common global i32 0, align 4
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@j = common global i32 0, align 4
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@.str = private unnamed_addr constant [8 x i8] c"%i %i \0A\00", align 1
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define void @foo(i32* %p, i32 %i, i32 %j) nounwind {
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entry:
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%p.addr = alloca i32*, align 4
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%i.addr = alloca i32, align 4
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%j.addr = alloca i32, align 4
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store i32* %p, i32** %p.addr, align 4
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store i32 %i, i32* %i.addr, align 4
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store i32 %j, i32* %j.addr, align 4
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%0 = load i32* %j.addr, align 4
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%1 = load i32** %p.addr, align 4
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%2 = load i32* %i.addr, align 4
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%add.ptr = getelementptr inbounds i32* %1, i32 %2
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store i32 %0, i32* %add.ptr, align 4
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ret void
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}
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define i32 @main() nounwind {
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entry:
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; 1: main:
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; 1: 1: .word -797992
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; 1: li ${{[0-9]+}}, 12
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; 1: sll ${{[0-9]+}}, ${{[0-9]+}}, 16
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; 1: addu ${{[0-9]+}}, ${{[0-9]+}}, ${{[0-9]+}}
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; 2: move $sp, ${{[0-9]+}}
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; 2: addu ${{[0-9]+}}, ${{[0-9]+}}, ${{[0-9]+}}
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; 1: li ${{[0-9]+}}, 6
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; 1: sll ${{[0-9]+}}, ${{[0-9]+}}, 16
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; 1: addu ${{[0-9]+}}, ${{[0-9]+}}, ${{[0-9]+}}
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; 2: move $sp, ${{[0-9]+}}
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; 2: addu ${{[0-9]+}}, ${{[0-9]+}}, ${{[0-9]+}}
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; 1: addiu ${{[0-9]+}}, ${{[0-9]+}}, 6800
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; 1: li ${{[0-9]+}}, 1
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; 1: sll ${{[0-9]+}}, ${{[0-9]+}}, 16
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; 2: li ${{[0-9]+}}, 34463
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%retval = alloca i32, align 4
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%one = alloca [100000 x i32], align 4
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%two = alloca [100000 x i32], align 4
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store i32 0, i32* %retval
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%arrayidx = getelementptr inbounds [100000 x i32]* %one, i32 0, i32 0
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call void @foo(i32* %arrayidx, i32 50, i32 9999)
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%arrayidx1 = getelementptr inbounds [100000 x i32]* %two, i32 0, i32 0
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call void @foo(i32* %arrayidx1, i32 99999, i32 5555)
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%arrayidx2 = getelementptr inbounds [100000 x i32]* %one, i32 0, i32 50
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%0 = load i32* %arrayidx2, align 4
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store i32 %0, i32* @i, align 4
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%arrayidx3 = getelementptr inbounds [100000 x i32]* %two, i32 0, i32 99999
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%1 = load i32* %arrayidx3, align 4
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store i32 %1, i32* @j, align 4
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%2 = load i32* @i, align 4
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%3 = load i32* @j, align 4
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%call = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([8 x i8]* @.str, i32 0, i32 0), i32 %2, i32 %3)
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ret i32 0
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}
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declare i32 @printf(i8*, ...)
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