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Fix a bug in X86InstrInfo::convertToThreeAddress that caused it to codegen:

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leal    (,%rcx,8), %rcx
It should be
leal    (,%rcx,8), %ecx


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41735 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng 2007-09-06 00:14:41 +00:00
parent 399ea50dc3
commit 61d9c861fd
2 changed files with 64 additions and 25 deletions
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40
lib/Target/X86/X86InstrInfo.cpp
View File

@ -210,39 +210,30 @@ X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
}
case X86::SHL16ri: {
assert(MI->getNumOperands() == 3 && "Unknown shift instruction!");
// NOTE: LEA doesn't produce flags like shift does, but LLVM never uses
// the flags produced by a shift yet, so this is safe.
unsigned Dest = MI->getOperand(0).getReg();
unsigned Src = MI->getOperand(1).getReg();
unsigned ShAmt = MI->getOperand(2).getImm();
if (ShAmt == 0 || ShAmt >= 4) return 0;
// NOTE: LEA doesn't produce flags like shift does, but LLVM never uses
// the flags produced by a shift yet, so this is safe.
unsigned Dest = MI->getOperand(0).getReg();
unsigned Src = MI->getOperand(1).getReg();
unsigned ShAmt = MI->getOperand(2).getImm();
if (ShAmt == 0 || ShAmt >= 4) return 0;
if (DisableLEA16) {
// If 16-bit LEA is disabled, use 32-bit LEA via subregisters.
SSARegMap *RegMap = MFI->getParent()->getSSARegMap();
unsigned Opc, leaInReg, leaOutReg;
MVT::ValueType leaVT;
if (TM.getSubtarget<X86Subtarget>().is64Bit()) {
Opc = X86::LEA64_32r;
leaVT = MVT::i64;
leaInReg = RegMap->createVirtualRegister(&X86::GR64RegClass);
leaOutReg = RegMap->createVirtualRegister(&X86::GR64RegClass);
} else {
Opc = X86::LEA32r;
leaVT = MVT::i32;
leaInReg = RegMap->createVirtualRegister(&X86::GR32RegClass);
leaOutReg = RegMap->createVirtualRegister(&X86::GR32RegClass);
}
unsigned Opc = TM.getSubtarget<X86Subtarget>().is64Bit()
? X86::LEA64_32r : X86::LEA32r;
unsigned leaInReg = RegMap->createVirtualRegister(&X86::GR32RegClass);
unsigned leaOutReg = RegMap->createVirtualRegister(&X86::GR32RegClass);
MachineInstr *Ins = NULL, *Ext = NULL;
Ins = BuildMI(get(X86::INSERT_SUBREG), leaInReg).addReg(Src).addImm(2);
MachineInstr *Ins =
BuildMI(get(X86::INSERT_SUBREG), leaInReg).addReg(Src).addImm(2);
Ins->copyKillDeadInfo(MI);
NewMI = BuildMI(get(Opc), leaOutReg)
.addReg(0).addImm(1 << ShAmt).addReg(leaInReg).addImm(0);
Ext = BuildMI(get(X86::EXTRACT_SUBREG), Dest).addReg(leaOutReg).addImm(2);
MachineInstr *Ext =
BuildMI(get(X86::EXTRACT_SUBREG), Dest).addReg(leaOutReg).addImm(2);
Ext->copyKillDeadInfo(MI);
MFI->insert(MBBI, Ins); // Insert the insert_subreg
@ -250,8 +241,7 @@ X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
LV.addVirtualRegisterKilled(leaInReg, NewMI);
MFI->insert(MBBI, NewMI); // Insert the new inst
LV.addVirtualRegisterKilled(leaOutReg, Ext);
MFI->insert(MBBI, Ext); // Insert the extract_subreg
MFI->insert(MBBI, Ext); // Insert the extract_subreg
return Ext;
} else {
NewMI = BuildMI(get(X86::LEA16r), Dest)

49
test/CodeGen/X86/2007-09-05-InvalidAsm.ll Normal file
View File

@ -0,0 +1,49 @@
; RUN: llvm-as < %s | llc -mtriple=x86_64-apple-darwin -x86-asm-syntax=intel | not grep {lea\[\[:space:\]\]R}
%struct.AGenericCall = type { %struct.AGenericManager*, %struct.ComponentParameters*, i32* }
%struct.AGenericManager = type <{ i8 }>
%struct.ComponentInstanceRecord = type opaque
%struct.ComponentParameters = type { [1 x i64] }
define i32 @_ZN12AGenericCall10MapIDPtrAtEsRP23ComponentInstanceRecord(%struct.AGenericCall* %this, i16 signext %param, %struct.ComponentInstanceRecord** %instance) {
entry:
%tmp4 = icmp slt i16 %param, 0 ; <i1> [#uses=1]
br i1 %tmp4, label %cond_true, label %cond_next
cond_true: ; preds = %entry
%tmp1415 = shl i16 %param, 3 ; <i16> [#uses=1]
%tmp17 = getelementptr %struct.AGenericCall* %this, i32 0, i32 1 ; <%struct.ComponentParameters**> [#uses=1]
%tmp18 = load %struct.ComponentParameters** %tmp17, align 8 ; <%struct.ComponentParameters*> [#uses=1]
%tmp1920 = bitcast %struct.ComponentParameters* %tmp18 to i8* ; <i8*> [#uses=1]
%tmp212223 = sext i16 %tmp1415 to i64 ; <i64> [#uses=1]
%tmp24 = getelementptr i8* %tmp1920, i64 %tmp212223 ; <i8*> [#uses=1]
%tmp2425 = bitcast i8* %tmp24 to i64* ; <i64*> [#uses=1]
%tmp28 = load i64* %tmp2425, align 8 ; <i64> [#uses=1]
%tmp2829 = inttoptr i64 %tmp28 to i32* ; <i32*> [#uses=1]
%tmp31 = getelementptr %struct.AGenericCall* %this, i32 0, i32 2 ; <i32**> [#uses=1]
store i32* %tmp2829, i32** %tmp31, align 8
br label %cond_next
cond_next: ; preds = %cond_true, %entry
%tmp4243 = shl i16 %param, 3 ; <i16> [#uses=1]
%tmp46 = getelementptr %struct.AGenericCall* %this, i32 0, i32 1 ; <%struct.ComponentParameters**> [#uses=1]
%tmp47 = load %struct.ComponentParameters** %tmp46, align 8 ; <%struct.ComponentParameters*> [#uses=1]
%tmp4849 = bitcast %struct.ComponentParameters* %tmp47 to i8* ; <i8*> [#uses=1]
%tmp505152 = sext i16 %tmp4243 to i64 ; <i64> [#uses=1]
%tmp53 = getelementptr i8* %tmp4849, i64 %tmp505152 ; <i8*> [#uses=1]
%tmp5354 = bitcast i8* %tmp53 to i64* ; <i64*> [#uses=1]
%tmp58 = load i64* %tmp5354, align 8 ; <i64> [#uses=1]
%tmp59 = icmp eq i64 %tmp58, 0 ; <i1> [#uses=1]
br i1 %tmp59, label %UnifiedReturnBlock, label %cond_true63
cond_true63: ; preds = %cond_next
%tmp65 = getelementptr %struct.AGenericCall* %this, i32 0, i32 0 ; <%struct.AGenericManager**> [#uses=1]
%tmp66 = load %struct.AGenericManager** %tmp65, align 8 ; <%struct.AGenericManager*> [#uses=1]
%tmp69 = tail call i32 @_ZN15AGenericManager24DefaultComponentInstanceERP23ComponentInstanceRecord( %struct.AGenericManager* %tmp66, %struct.ComponentInstanceRecord** %instance ) ; <i32> [#uses=1]
ret i32 %tmp69
UnifiedReturnBlock: ; preds = %cond_next
ret i32 undef
}
declare i32 @_ZN15AGenericManager24DefaultComponentInstanceERP23ComponentInstanceRecord(%struct.AGenericManager*, %struct.ComponentInstanceRecord**)