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The Mips64InstrInfo.td definitions DynAlloc64 LEA_ADDiu64

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were using a class defined for 32 bit instructions and 
thus the instruction was for addiu instead of daddiu.

This was corrected by adding the instruction opcode as a 
field in the  base class to be filled in by the defs.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161359 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jack Carter 2012-08-06 23:29:06 +00:00
parent eda3fc6734
commit 61de70d98e
3 changed files with 28 additions and 14 deletions
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8
lib/Target/Mips/Mips64InstrInfo.td
View File

@ -208,13 +208,11 @@ def DCLO : CountLeading1<0x25, "dclo", CPU64Regs>;
def DSBH : SubwordSwap<0x24, 0x2, "dsbh", CPU64Regs>;
def DSHD : SubwordSwap<0x24, 0x5, "dshd", CPU64Regs>;
def LEA_ADDiu64 : EffectiveAddress<"daddiu\t$rt, $addr", CPU64Regs, mem_ea_64>;
def LEA_ADDiu64 : EffectiveAddress<0x19,"daddiu\t$rt, $addr", CPU64Regs, mem_ea_64>;
}
let Uses = [SP_64], DecoderNamespace = "Mips64" in
def DynAlloc64 : EffectiveAddress<"daddiu\t$rt, $addr", CPU64Regs, mem_ea_64>,
Requires<[IsN64, HasStandardEncoding]> {
let isCodeGenOnly = 1;
}
def DynAlloc64 : EffectiveAddress<0x19,"daddiu\t$rt, $addr", CPU64Regs, mem_ea_64>,
Requires<[IsN64, HasStandardEncoding]>;
let DecoderNamespace = "Mips64" in {
def RDHWR64 : ReadHardware<CPU64Regs, HWRegs64>;

16
lib/Target/Mips/MipsInstrInfo.td
View File

@ -722,9 +722,11 @@ class MoveToLOHI<bits<6> func, string instr_asm, RegisterClass RC,
let neverHasSideEffects = 1;
}
class EffectiveAddress<string instr_asm, RegisterClass RC, Operand Mem> :
FMem<0x09, (outs RC:$rt), (ins Mem:$addr),
instr_asm, [(set RC:$rt, addr:$addr)], IIAlu>;
class EffectiveAddress<bits<6> opc, string instr_asm, RegisterClass RC, Operand Mem> :
FMem<opc, (outs RC:$rt), (ins Mem:$addr),
instr_asm, [(set RC:$rt, addr:$addr)], IIAlu> {
let isCodeGenOnly = 1;
}
// Count Leading Ones/Zeros in Word
class CountLeading0<bits<6> func, string instr_asm, RegisterClass RC>:
@ -1045,17 +1047,13 @@ let addr=0 in
// instructions. The same not happens for stack address copies, so an
// add op with mem ComplexPattern is used and the stack address copy
// can be matched. It's similar to Sparc LEA_ADDRi
def LEA_ADDiu : EffectiveAddress<"addiu\t$rt, $addr", CPURegs, mem_ea> {
let isCodeGenOnly = 1;
}
def LEA_ADDiu : EffectiveAddress<0x09,"addiu\t$rt, $addr", CPURegs, mem_ea>;
// DynAlloc node points to dynamically allocated stack space.
// $sp is added to the list of implicitly used registers to prevent dead code
// elimination from removing instructions that modify $sp.
let Uses = [SP] in
def DynAlloc : EffectiveAddress<"addiu\t$rt, $addr", CPURegs, mem_ea> {
let isCodeGenOnly = 1;
}
def DynAlloc : EffectiveAddress<0x09,"addiu\t$rt, $addr", CPURegs, mem_ea>;
// MADD*/MSUB*
def MADD : MArithR<0, "madd", MipsMAdd, 1>;

18
test/MC/Mips/lea_64.ll Normal file
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@ -0,0 +1,18 @@
; RUN: llc -march=mips64el -filetype=obj -mcpu=mips64r2 %s -o - \
; RUN: | llvm-objdump -disassemble -triple mips64el - \
; RUN: | FileCheck %s
@p = external global i32*
define void @f1() nounwind {
entry:
; CHECK: .text:
; CHECK-NOT: addiu {{[0-9,a-f]+}}, {{[0-9,a-f]+}}, {{[0-9]+}}
%a = alloca [10 x i32], align 4
%arraydecay = getelementptr inbounds [10 x i32]* %a, i64 0, i64 0
store i32* %arraydecay, i32** @p, align 8
ret void
; CHECK: jr $ra
}