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The Mips64InstrInfo.td definitions DynAlloc64 LEA_ADDiu64
were using a class defined for 32 bit instructions and thus the instruction was for addiu instead of daddiu. This was corrected by adding the instruction opcode as a field in the base class to be filled in by the defs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161359 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -208,13 +208,11 @@ def DCLO : CountLeading1<0x25, "dclo", CPU64Regs>;
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def DSBH : SubwordSwap<0x24, 0x2, "dsbh", CPU64Regs>;
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def DSHD : SubwordSwap<0x24, 0x5, "dshd", CPU64Regs>;
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def LEA_ADDiu64 : EffectiveAddress<"daddiu\t$rt, $addr", CPU64Regs, mem_ea_64>;
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def LEA_ADDiu64 : EffectiveAddress<0x19,"daddiu\t$rt, $addr", CPU64Regs, mem_ea_64>;
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}
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let Uses = [SP_64], DecoderNamespace = "Mips64" in
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def DynAlloc64 : EffectiveAddress<"daddiu\t$rt, $addr", CPU64Regs, mem_ea_64>,
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Requires<[IsN64, HasStandardEncoding]> {
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let isCodeGenOnly = 1;
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}
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def DynAlloc64 : EffectiveAddress<0x19,"daddiu\t$rt, $addr", CPU64Regs, mem_ea_64>,
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Requires<[IsN64, HasStandardEncoding]>;
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let DecoderNamespace = "Mips64" in {
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def RDHWR64 : ReadHardware<CPU64Regs, HWRegs64>;
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@ -722,9 +722,11 @@ class MoveToLOHI<bits<6> func, string instr_asm, RegisterClass RC,
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let neverHasSideEffects = 1;
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}
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class EffectiveAddress<string instr_asm, RegisterClass RC, Operand Mem> :
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FMem<0x09, (outs RC:$rt), (ins Mem:$addr),
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instr_asm, [(set RC:$rt, addr:$addr)], IIAlu>;
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class EffectiveAddress<bits<6> opc, string instr_asm, RegisterClass RC, Operand Mem> :
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FMem<opc, (outs RC:$rt), (ins Mem:$addr),
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instr_asm, [(set RC:$rt, addr:$addr)], IIAlu> {
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let isCodeGenOnly = 1;
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}
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// Count Leading Ones/Zeros in Word
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class CountLeading0<bits<6> func, string instr_asm, RegisterClass RC>:
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@ -1045,17 +1047,13 @@ let addr=0 in
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// instructions. The same not happens for stack address copies, so an
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// add op with mem ComplexPattern is used and the stack address copy
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// can be matched. It's similar to Sparc LEA_ADDRi
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def LEA_ADDiu : EffectiveAddress<"addiu\t$rt, $addr", CPURegs, mem_ea> {
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let isCodeGenOnly = 1;
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}
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def LEA_ADDiu : EffectiveAddress<0x09,"addiu\t$rt, $addr", CPURegs, mem_ea>;
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// DynAlloc node points to dynamically allocated stack space.
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// $sp is added to the list of implicitly used registers to prevent dead code
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// elimination from removing instructions that modify $sp.
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let Uses = [SP] in
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def DynAlloc : EffectiveAddress<"addiu\t$rt, $addr", CPURegs, mem_ea> {
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let isCodeGenOnly = 1;
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}
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def DynAlloc : EffectiveAddress<0x09,"addiu\t$rt, $addr", CPURegs, mem_ea>;
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// MADD*/MSUB*
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def MADD : MArithR<0, "madd", MipsMAdd, 1>;
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18
test/MC/Mips/lea_64.ll
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18
test/MC/Mips/lea_64.ll
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@ -0,0 +1,18 @@
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; RUN: llc -march=mips64el -filetype=obj -mcpu=mips64r2 %s -o - \
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; RUN: | llvm-objdump -disassemble -triple mips64el - \
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; RUN: | FileCheck %s
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@p = external global i32*
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define void @f1() nounwind {
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entry:
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; CHECK: .text:
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; CHECK-NOT: addiu {{[0-9,a-f]+}}, {{[0-9,a-f]+}}, {{[0-9]+}}
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%a = alloca [10 x i32], align 4
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%arraydecay = getelementptr inbounds [10 x i32]* %a, i64 0, i64 0
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store i32* %arraydecay, i32** @p, align 8
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ret void
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; CHECK: jr $ra
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}
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