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Move pass configuration out of pass constructors: BranchFolderPass
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150095 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -42,9 +42,13 @@ protected:
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bool Initialized; // Flagged after all passes are configured.
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bool Initialized; // Flagged after all passes are configured.
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// Target Pass Options
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// Target Pass Options
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// Targets provide a default setting, user flags override.
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//
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//
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bool DisableVerify;
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bool DisableVerify;
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/// Default setting for -enable-tail-merge on this target.
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bool EnableTailMerge;
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public:
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public:
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TargetPassConfig(TargetMachine *tm, PassManagerBase &pm);
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TargetPassConfig(TargetMachine *tm, PassManagerBase &pm);
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// Dummy constructor.
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// Dummy constructor.
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@ -67,7 +71,10 @@ public:
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CodeGenOpt::Level getOptLevel() const { return TM->getOptLevel(); }
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CodeGenOpt::Level getOptLevel() const { return TM->getOptLevel(); }
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void setDisableVerify(bool disable) { DisableVerify = disable; }
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void setDisableVerify(bool Disable) { setOpt(DisableVerify, Disable); }
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bool getEnableTailMerge() const { return EnableTailMerge; }
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void setEnableTailMerge(bool Enable) { setOpt(EnableTailMerge, Enable); }
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/// Add common target configurable passes that perform LLVM IR to IR
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/// Add common target configurable passes that perform LLVM IR to IR
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/// transforms following machine independent optimization.
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/// transforms following machine independent optimization.
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@ -118,10 +125,6 @@ protected:
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return false;
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return false;
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}
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}
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/// getEnableTailMergeDefault - the default setting for -enable-tail-merge
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/// on this target. User flag overrides.
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virtual bool getEnableTailMergeDefault() const { return true; }
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/// addPreSched2 - This method may be implemented by targets that want to
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/// addPreSched2 - This method may be implemented by targets that want to
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/// run passes after prolog-epilog insertion and before the second instruction
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/// run passes after prolog-epilog insertion and before the second instruction
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/// scheduling pass. This should return true if -print-machineinstrs should
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/// scheduling pass. This should return true if -print-machineinstrs should
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@ -274,7 +277,7 @@ namespace llvm {
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/// optimizations to delete branches to branches, eliminate branches to
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/// optimizations to delete branches to branches, eliminate branches to
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/// successor blocks (creating fall throughs), and eliminating branches over
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/// successor blocks (creating fall throughs), and eliminating branches over
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/// branches.
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/// branches.
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FunctionPass *createBranchFoldingPass(bool DefaultEnableTailMerge);
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extern char &BranchFolderPassID;
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/// TailDuplicate Pass - Duplicate blocks with unconditional branches
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/// TailDuplicate Pass - Duplicate blocks with unconditional branches
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/// into tails of their predecessors.
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/// into tails of their predecessors.
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@ -71,6 +71,7 @@ void initializeBasicCallGraphPass(PassRegistry&);
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void initializeBlockExtractorPassPass(PassRegistry&);
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void initializeBlockExtractorPassPass(PassRegistry&);
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void initializeBlockFrequencyInfoPass(PassRegistry&);
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void initializeBlockFrequencyInfoPass(PassRegistry&);
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void initializeBlockPlacementPass(PassRegistry&);
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void initializeBlockPlacementPass(PassRegistry&);
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void initializeBranchFolderPassPass(PassRegistry&);
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void initializeBranchProbabilityInfoPass(PassRegistry&);
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void initializeBranchProbabilityInfoPass(PassRegistry&);
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void initializeBreakCriticalEdgesPass(PassRegistry&);
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void initializeBreakCriticalEdgesPass(PassRegistry&);
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void initializeCFGOnlyPrinterPass(PassRegistry&);
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void initializeCFGOnlyPrinterPass(PassRegistry&);
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@ -61,29 +61,33 @@ TailMergeSize("tail-merge-size",
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namespace {
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namespace {
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/// BranchFolderPass - Wrap branch folder in a machine function pass.
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/// BranchFolderPass - Wrap branch folder in a machine function pass.
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class BranchFolderPass : public MachineFunctionPass,
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class BranchFolderPass : public MachineFunctionPass {
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public BranchFolder {
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public:
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public:
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static char ID;
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static char ID;
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explicit BranchFolderPass(bool defaultEnableTailMerge)
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explicit BranchFolderPass(): MachineFunctionPass(ID) {}
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: MachineFunctionPass(ID), BranchFolder(defaultEnableTailMerge, true) {}
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virtual bool runOnMachineFunction(MachineFunction &MF);
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virtual bool runOnMachineFunction(MachineFunction &MF);
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virtual const char *getPassName() const { return "Control Flow Optimizer"; }
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virtual void getAnalysisUsage(AnalysisUsage &AU) const {
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AU.addRequired<TargetPassConfig>();
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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};
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};
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}
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}
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char BranchFolderPass::ID = 0;
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char BranchFolderPass::ID = 0;
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char &llvm::BranchFolderPassID = BranchFolderPass::ID;
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FunctionPass *llvm::createBranchFoldingPass(bool DefaultEnableTailMerge) {
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INITIALIZE_PASS(BranchFolderPass, "branch-folder",
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return new BranchFolderPass(DefaultEnableTailMerge);
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"Control Flow Optimizer", false, false)
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}
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bool BranchFolderPass::runOnMachineFunction(MachineFunction &MF) {
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bool BranchFolderPass::runOnMachineFunction(MachineFunction &MF) {
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return OptimizeFunction(MF,
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TargetPassConfig *PassConfig = &getAnalysis<TargetPassConfig>();
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MF.getTarget().getInstrInfo(),
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BranchFolder Folder(PassConfig->getEnableTailMerge(), /*CommonHoist=*/true);
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MF.getTarget().getRegisterInfo(),
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return Folder.OptimizeFunction(MF,
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getAnalysisIfAvailable<MachineModuleInfo>());
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MF.getTarget().getInstrInfo(),
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MF.getTarget().getRegisterInfo(),
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getAnalysisIfAvailable<MachineModuleInfo>());
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}
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}
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@ -19,6 +19,7 @@ using namespace llvm;
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/// initializeCodeGen - Initialize all passes linked into the CodeGen library.
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/// initializeCodeGen - Initialize all passes linked into the CodeGen library.
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void llvm::initializeCodeGen(PassRegistry &Registry) {
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void llvm::initializeCodeGen(PassRegistry &Registry) {
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initializeBranchFolderPassPass(Registry);
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initializeCalculateSpillWeightsPass(Registry);
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initializeCalculateSpillWeightsPass(Registry);
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initializeDeadMachineInstructionElimPass(Registry);
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initializeDeadMachineInstructionElimPass(Registry);
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initializeGCModuleInfoPass(Registry);
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initializeGCModuleInfoPass(Registry);
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@ -83,6 +83,8 @@ char TargetPassConfig::ID = 0;
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// Out of line virtual method.
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// Out of line virtual method.
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TargetPassConfig::~TargetPassConfig() {}
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TargetPassConfig::~TargetPassConfig() {}
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// Out of line constructor provides default values for pass options and
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// registers all common codegen passes.
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TargetPassConfig::TargetPassConfig(TargetMachine *tm, PassManagerBase &pm)
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TargetPassConfig::TargetPassConfig(TargetMachine *tm, PassManagerBase &pm)
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: ImmutablePass(ID), TM(tm), PM(pm), Initialized(false),
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: ImmutablePass(ID), TM(tm), PM(pm), Initialized(false),
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DisableVerify(false),
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DisableVerify(false),
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@ -257,7 +259,7 @@ void TargetPassConfig::addMachinePasses() {
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// Branch folding must be run after regalloc and prolog/epilog insertion.
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// Branch folding must be run after regalloc and prolog/epilog insertion.
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if (getOptLevel() != CodeGenOpt::None && !DisableBranchFold) {
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if (getOptLevel() != CodeGenOpt::None && !DisableBranchFold) {
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PM.add(createBranchFoldingPass(getEnableTailMergeDefault()));
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addPass(BranchFolderPassID);
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printNoVerify("After BranchFolding");
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printNoVerify("After BranchFolding");
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}
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}
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@ -359,7 +359,7 @@ bool PTXPassConfig::addCodeGenPasses(MCContext *&OutContext) {
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// Branch folding must be run after regalloc and prolog/epilog insertion.
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// Branch folding must be run after regalloc and prolog/epilog insertion.
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if (getOptLevel() != CodeGenOpt::None) {
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if (getOptLevel() != CodeGenOpt::None) {
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PM.add(createBranchFoldingPass(getEnableTailMergeDefault()));
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addPass(BranchFolderPassID);
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printNoVerify("After BranchFolding");
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printNoVerify("After BranchFolding");
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}
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}
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@ -78,13 +78,18 @@ public:
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}
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}
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virtual bool addInstSelector();
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virtual bool addInstSelector();
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virtual bool getEnableTailMergeDefault() const;
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virtual bool addPreEmitPass();
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virtual bool addPreEmitPass();
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};
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};
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} // namespace
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} // namespace
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TargetPassConfig *PPCTargetMachine::createPassConfig(PassManagerBase &PM) {
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TargetPassConfig *PPCTargetMachine::createPassConfig(PassManagerBase &PM) {
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return new PPCPassConfig(this, PM);
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TargetPassConfig *PassConfig = new PPCPassConfig(this, PM);
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// Override this for PowerPC. Tail merging happily breaks up instruction issue
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// groups, which typically degrades performance.
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PassConfig->setEnableTailMerge(false);
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return PassConfig;
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}
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}
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bool PPCPassConfig::addInstSelector() {
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bool PPCPassConfig::addInstSelector() {
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@ -93,10 +98,6 @@ bool PPCPassConfig::addInstSelector() {
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return false;
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return false;
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}
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}
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/// Override this for PowerPC. Tail merging happily breaks up instruction issue
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/// groups, which typically degrades performance.
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bool PPCPassConfig::getEnableTailMergeDefault() const { return false; }
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bool PPCPassConfig::addPreEmitPass() {
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bool PPCPassConfig::addPreEmitPass() {
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// Must run branch selection immediately preceding the asm printer.
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// Must run branch selection immediately preceding the asm printer.
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PM.add(createPPCBranchSelectionPass());
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PM.add(createPPCBranchSelectionPass());
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