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[DAGCombine] Disable select(c, load,load) for indexed loads

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This turned up after r235333, but was a pre-existing bug. The optimization
which transforms select(c, load, load) into a load of a select of the addresses
does not handle indexed loads (pre/post inc/dec). However, it did not check for
them either, leading to a crash if it tried to transform one of them.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235497 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Hal Finkel 2015-04-22 11:32:25 +00:00
parent 21249eca6b
commit 61ffda59f9
2 changed files with 66 additions and 0 deletions
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3
lib/CodeGen/SelectionDAG/DAGCombiner.cpp
View File

@ -12799,6 +12799,9 @@ bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDValue LHS,
if (LHS.getOperand(0) != RHS.getOperand(0) ||
// Do not let this transformation reduce the number of volatile loads.
LLD->isVolatile() || RLD->isVolatile() ||
// FIXME: If either is a pre/post inc/dec load,
// we'd need to split out the address adjustment.
LLD->isIndexed() || RLD->isIndexed() ||
// If this is an EXTLOAD, the VT's must match.
LLD->getMemoryVT() != RLD->getMemoryVT() ||
// If this is an EXTLOAD, the kind of extension must match.

63
test/CodeGen/PowerPC/preinc-ld-sel-crash.ll Normal file
View File

@ -0,0 +1,63 @@
; RUN: llc < %s | FileCheck %s
target datalayout = "E-m:e-i64:64-n32:64"
target triple = "powerpc64-bgq-linux"
%t1 = type { %t2*, %t3* }
%t2 = type <{ %t3*, i32, [4 x i8] }>
%t3 = type { %t3* }
@_ZN4Foam10SLListBase13endConstIter_E = external global %t1
define void @_ZN4FoamrsIbEERNS_7IstreamES2_RNS_4ListIT_EE() #0 {
entry:
switch i32 undef, label %if.else82 [
i32 9, label %if.then
i32 6, label %invoke.cont10
i32 1, label %invoke.cont61
]
if.then: ; preds = %entry
unreachable
invoke.cont10: ; preds = %entry
unreachable
invoke.cont61: ; preds = %entry
br i1 undef, label %if.end75, label %if.then64
if.then64: ; preds = %invoke.cont61
unreachable
if.end75: ; preds = %invoke.cont61
br i1 undef, label %if.then17.i, label %if.then.i181
if.then.i181: ; preds = %if.end75
unreachable
if.then17.i: ; preds = %if.end75
%tobool.i.i.i = icmp eq i32 undef, 0
%0 = load i64*, i64** undef, align 8
%agg.tmp.sroa.3.0.copyload33.in.i = select i1 %tobool.i.i.i, i64* bitcast (%t3** getelementptr inbounds (%t1, %t1* @_ZN4Foam10SLListBase13endConstIter_E, i64 0, i32 1) to i64*), i64* %0
%agg.tmp.sroa.3.0.copyload33.i = load i64, i64* %agg.tmp.sroa.3.0.copyload33.in.i, align 8
%1 = inttoptr i64 %agg.tmp.sroa.3.0.copyload33.i to %t3*
%2 = load %t3*, %t3** getelementptr inbounds (%t1, %t1* @_ZN4Foam10SLListBase13endConstIter_E, i64 0, i32 1), align 8
%cmp.i37.i = icmp eq %t3* %1, %2
br i1 %cmp.i37.i, label %invoke.cont79, label %for.body.lr.ph.i
; CHECK-LABEL: @_ZN4FoamrsIbEERNS_7IstreamES2_RNS_4ListIT_EE
for.body.lr.ph.i: ; preds = %if.then17.i
br label %for.body.i
for.body.i: ; preds = %for.body.i, %for.body.lr.ph.i
br i1 undef, label %invoke.cont79, label %for.body.i
invoke.cont79: ; preds = %for.body.i, %if.then17.i
unreachable
if.else82: ; preds = %entry
ret void
}
attributes #0 = { "target-cpu"="a2q" }