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Change some places that were checking for AVX OR SSE1/2 to use hasXMM/hasXMMInt instead. Also fix one place that checked SSE3, but accidentally excluded AVX to use hasSSE3orAVX. This is a step towards removing the AVX hack from the X86Subtarget.h

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147764 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Craig Topper 2012-01-09 02:28:15 +00:00
parent 1fe9737eb4
commit 6202e45d53
2 changed files with 6 additions and 6 deletions
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8
lib/Target/X86/X86FastISel.cpp
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@ -60,8 +60,8 @@ public:
explicit X86FastISel(FunctionLoweringInfo &funcInfo) : FastISel(funcInfo) {
Subtarget = &TM.getSubtarget<X86Subtarget>();
StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP;
X86ScalarSSEf64 = Subtarget->hasSSE2() || Subtarget->hasAVX();
X86ScalarSSEf32 = Subtarget->hasSSE1() || Subtarget->hasAVX();
X86ScalarSSEf64 = Subtarget->hasXMMInt();
X86ScalarSSEf32 = Subtarget->hasXMM();
}
virtual bool TargetSelectInstruction(const Instruction *I);
@ -837,8 +837,8 @@ bool X86FastISel::X86SelectLoad(const Instruction *I) {
static unsigned X86ChooseCmpOpcode(EVT VT, const X86Subtarget *Subtarget) {
bool HasAVX = Subtarget->hasAVX();
bool X86ScalarSSEf32 = HasAVX || Subtarget->hasSSE1();
bool X86ScalarSSEf64 = HasAVX || Subtarget->hasSSE2();
bool X86ScalarSSEf32 = Subtarget->hasXMM();
bool X86ScalarSSEf64 = Subtarget->hasXMMInt();
switch (VT.getSimpleVT().SimpleTy) {
default: return 0;

4
lib/Target/X86/X86ISelLowering.cpp
View File

@ -7630,7 +7630,7 @@ SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
SDValue Result;
if (Subtarget->hasSSE3()) {
if (Subtarget->hasSSE3orAVX()) {
// FIXME: The 'haddpd' instruction may be slower than 'movhlps + addsd'.
Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub);
} else {
@ -12894,7 +12894,7 @@ static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
VT != MVT::f80 && DAG.getTargetLoweringInfo().isTypeLegal(VT) &&
(Subtarget->hasXMMInt() ||
(Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) {
(Subtarget->hasXMM() && VT.getScalarType() == MVT::f32))) {
ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
unsigned Opcode = 0;