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https://github.com/c64scene-ar/llvm-6502.git
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Turn on -neon-reg-sequence by default.
Using NEON load / store multiple instructions will no longer create gobs of vmov of D registers! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103960 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng
parent
525a3a67c1
commit
6206124250
@ -37,7 +37,8 @@ using namespace llvm;
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static cl::opt<bool>
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UseRegSeq("neon-reg-sequence", cl::Hidden,
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cl::desc("Use reg_sequence to model ld / st of multiple neon regs"));
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cl::desc("Use reg_sequence to model ld / st of multiple neon regs"),
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cl::init(true));
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//===--------------------------------------------------------------------===//
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/// ARMDAGToDAGISel - ARM specific code to select ARM machine
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170
test/CodeGen/ARM/reg_sequence.ll
Normal file
170
test/CodeGen/ARM/reg_sequence.ll
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@ -0,0 +1,170 @@
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; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
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; Implementing vld / vst as REG_SEQUENCE eliminates the extra vmov's.
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%struct.int16x8_t = type { <8 x i16> }
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%struct.int32x4_t = type { <4 x i32> }
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%struct.__neon_int8x8x3_t = type { <8 x i8>, <8 x i8>, <8 x i8> }
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%struct.__neon_int16x8x2_t = type { <8 x i16>, <8 x i16> }
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%struct.__neon_int32x4x2_t = type { <4 x i32>, <4 x i32> }
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define arm_apcscc void @t1(i16* %i_ptr, i16* %o_ptr, %struct.int32x4_t* nocapture %vT0ptr, %struct.int32x4_t* nocapture %vT1ptr) nounwind {
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entry:
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; CHECK: t1:
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; CHECK: vld1.16
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; CHECK-NOT: vmov d
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; CHECK: vmovl.s16
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; CHECK: vshrn.i32
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; CHECK: vshrn.i32
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; CHECK-NOT: vmov d
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; CHECK-NEXT: vst1.16
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%0 = getelementptr inbounds %struct.int32x4_t* %vT0ptr, i32 0, i32 0 ; <<4 x i32>*> [#uses=1]
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%1 = load <4 x i32>* %0, align 16 ; <<4 x i32>> [#uses=1]
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%2 = getelementptr inbounds %struct.int32x4_t* %vT1ptr, i32 0, i32 0 ; <<4 x i32>*> [#uses=1]
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%3 = load <4 x i32>* %2, align 16 ; <<4 x i32>> [#uses=1]
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%4 = bitcast i16* %i_ptr to i8* ; <i8*> [#uses=1]
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%5 = tail call <8 x i16> @llvm.arm.neon.vld1.v8i16(i8* %4) ; <<8 x i16>> [#uses=1]
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%6 = bitcast <8 x i16> %5 to <2 x double> ; <<2 x double>> [#uses=2]
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%7 = extractelement <2 x double> %6, i32 0 ; <double> [#uses=1]
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%8 = bitcast double %7 to <4 x i16> ; <<4 x i16>> [#uses=1]
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%9 = tail call <4 x i32> @llvm.arm.neon.vmovls.v4i32(<4 x i16> %8) ; <<4 x i32>> [#uses=1]
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%10 = extractelement <2 x double> %6, i32 1 ; <double> [#uses=1]
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%11 = bitcast double %10 to <4 x i16> ; <<4 x i16>> [#uses=1]
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%12 = tail call <4 x i32> @llvm.arm.neon.vmovls.v4i32(<4 x i16> %11) ; <<4 x i32>> [#uses=1]
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%13 = mul <4 x i32> %1, %9 ; <<4 x i32>> [#uses=1]
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%14 = mul <4 x i32> %3, %12 ; <<4 x i32>> [#uses=1]
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%15 = tail call <4 x i16> @llvm.arm.neon.vshiftn.v4i16(<4 x i32> %13, <4 x i32> <i32 -12, i32 -12, i32 -12, i32 -12>) ; <<4 x i16>> [#uses=1]
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%16 = tail call <4 x i16> @llvm.arm.neon.vshiftn.v4i16(<4 x i32> %14, <4 x i32> <i32 -12, i32 -12, i32 -12, i32 -12>) ; <<4 x i16>> [#uses=1]
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%17 = shufflevector <4 x i16> %15, <4 x i16> %16, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> ; <<8 x i16>> [#uses=1]
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%18 = bitcast i16* %o_ptr to i8* ; <i8*> [#uses=1]
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tail call void @llvm.arm.neon.vst1.v8i16(i8* %18, <8 x i16> %17)
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ret void
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}
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define arm_apcscc void @t2(i16* %i_ptr, i16* %o_ptr, %struct.int16x8_t* nocapture %vT0ptr, %struct.int16x8_t* nocapture %vT1ptr) nounwind {
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entry:
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; CHECK: t2:
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; CHECK: vld1.16
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; CHECK-NOT: vmov
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; CHECK: vmul.i16
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; CHECK: vld1.16
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; CHECK: vst1.16
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; CHECK-NOT: vmov
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; CHECK: vmul.i16
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; CHECK: vst1.16
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%0 = getelementptr inbounds %struct.int16x8_t* %vT0ptr, i32 0, i32 0 ; <<8 x i16>*> [#uses=1]
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%1 = load <8 x i16>* %0, align 16 ; <<8 x i16>> [#uses=1]
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%2 = getelementptr inbounds %struct.int16x8_t* %vT1ptr, i32 0, i32 0 ; <<8 x i16>*> [#uses=1]
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%3 = load <8 x i16>* %2, align 16 ; <<8 x i16>> [#uses=1]
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%4 = bitcast i16* %i_ptr to i8* ; <i8*> [#uses=1]
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%5 = tail call <8 x i16> @llvm.arm.neon.vld1.v8i16(i8* %4) ; <<8 x i16>> [#uses=1]
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%6 = getelementptr inbounds i16* %i_ptr, i32 8 ; <i16*> [#uses=1]
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%7 = bitcast i16* %6 to i8* ; <i8*> [#uses=1]
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%8 = tail call <8 x i16> @llvm.arm.neon.vld1.v8i16(i8* %7) ; <<8 x i16>> [#uses=1]
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%9 = mul <8 x i16> %1, %5 ; <<8 x i16>> [#uses=1]
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%10 = mul <8 x i16> %3, %8 ; <<8 x i16>> [#uses=1]
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%11 = bitcast i16* %o_ptr to i8* ; <i8*> [#uses=1]
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tail call void @llvm.arm.neon.vst1.v8i16(i8* %11, <8 x i16> %9)
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%12 = getelementptr inbounds i16* %o_ptr, i32 8 ; <i16*> [#uses=1]
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%13 = bitcast i16* %12 to i8* ; <i8*> [#uses=1]
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tail call void @llvm.arm.neon.vst1.v8i16(i8* %13, <8 x i16> %10)
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ret void
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}
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define <8 x i8> @t3(i8* %A, i8* %B) nounwind {
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; CHECK: t3:
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; CHECK: vld3.8
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; CHECK: vmul.i8
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; CHECK-NOT: vmov
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; CHECK: vst3.8
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%tmp1 = call %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3.v8i8(i8* %A) ; <%struct.__neon_int8x8x3_t> [#uses=2]
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%tmp2 = extractvalue %struct.__neon_int8x8x3_t %tmp1, 0 ; <<8 x i8>> [#uses=1]
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%tmp3 = extractvalue %struct.__neon_int8x8x3_t %tmp1, 2 ; <<8 x i8>> [#uses=1]
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%tmp4 = extractvalue %struct.__neon_int8x8x3_t %tmp1, 1 ; <<8 x i8>> [#uses=1]
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%tmp5 = sub <8 x i8> %tmp3, %tmp4
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%tmp6 = add <8 x i8> %tmp2, %tmp3 ; <<8 x i8>> [#uses=1]
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%tmp7 = mul <8 x i8> %tmp4, %tmp2
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tail call void @llvm.arm.neon.vst3.v8i8(i8* %B, <8 x i8> %tmp5, <8 x i8> %tmp6, <8 x i8> %tmp7)
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ret <8 x i8> %tmp4
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}
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define arm_apcscc void @t4(i32* %in, i32* %out) nounwind {
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entry:
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; CHECK: t4:
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; CHECK: vld2.32
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; CHECK-NOT: vmov
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; CHECK: vld2.32
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; CHECK-NOT: vmov
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; CHECK: bne
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%tmp1 = bitcast i32* %in to i8* ; <i8*> [#uses=1]
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%tmp2 = tail call %struct.__neon_int32x4x2_t @llvm.arm.neon.vld2.v4i32(i8* %tmp1) ; <%struct.__neon_int32x4x2_t> [#uses=2]
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%tmp3 = getelementptr inbounds i32* %in, i32 8 ; <i32*> [#uses=1]
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%tmp4 = bitcast i32* %tmp3 to i8* ; <i8*> [#uses=1]
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%tmp5 = tail call %struct.__neon_int32x4x2_t @llvm.arm.neon.vld2.v4i32(i8* %tmp4) ; <%struct.__neon_int32x4x2_t> [#uses=2]
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%tmp8 = bitcast i32* %out to i8* ; <i8*> [#uses=1]
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br i1 undef, label %return1, label %return2
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return1:
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; CHECK: %return1
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; CHECK-NOT: vmov
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; CHECK-NEXT: vadd.i32
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; CHECK-NEXT: vadd.i32
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; CHECK-NEXT: vst2.32
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%tmp52 = extractvalue %struct.__neon_int32x4x2_t %tmp2, 0 ; <<4 x i32>> [#uses=1]
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%tmp57 = extractvalue %struct.__neon_int32x4x2_t %tmp2, 1 ; <<4 x i32>> [#uses=1]
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%tmp = extractvalue %struct.__neon_int32x4x2_t %tmp5, 0 ; <<4 x i32>> [#uses=1]
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%tmp39 = extractvalue %struct.__neon_int32x4x2_t %tmp5, 1 ; <<4 x i32>> [#uses=1]
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%tmp6 = add <4 x i32> %tmp52, %tmp ; <<4 x i32>> [#uses=1]
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%tmp7 = add <4 x i32> %tmp57, %tmp39 ; <<4 x i32>> [#uses=1]
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tail call void @llvm.arm.neon.vst2.v4i32(i8* %tmp8, <4 x i32> %tmp6, <4 x i32> %tmp7)
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ret void
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return2:
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; CHECK: %return2
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; CHECK: vadd.i32
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; CHECK: vmov q1, q3
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; CHECK-NOT: vmov
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; CHECK: vst2.32 {d0, d1, d2, d3}
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%tmp100 = extractvalue %struct.__neon_int32x4x2_t %tmp2, 0 ; <<4 x i32>> [#uses=1]
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%tmp101 = extractvalue %struct.__neon_int32x4x2_t %tmp5, 1 ; <<4 x i32>> [#uses=1]
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%tmp102 = add <4 x i32> %tmp100, %tmp101 ; <<4 x i32>> [#uses=1]
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tail call void @llvm.arm.neon.vst2.v4i32(i8* %tmp8, <4 x i32> %tmp102, <4 x i32> %tmp101)
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call void @llvm.trap()
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unreachable
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}
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define <8 x i16> @t5(i16* %A, <8 x i16>* %B) nounwind {
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; CHECK: t5:
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; CHECK: vldmia
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; CHECK: vmov q1, q0
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; CHECK-NOT: vmov
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; CHECK: vld2.16 {d0[1], d2[1]}, [r0]
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; CHECK-NOT: vmov
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; CHECK: vadd.i16
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%tmp0 = bitcast i16* %A to i8* ; <i8*> [#uses=1]
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%tmp1 = load <8 x i16>* %B ; <<8 x i16>> [#uses=2]
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%tmp2 = call %struct.__neon_int16x8x2_t @llvm.arm.neon.vld2lane.v8i16(i8* %tmp0, <8 x i16> %tmp1, <8 x i16> %tmp1, i32 1) ; <%struct.__neon_int16x8x2_t> [#uses=2]
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%tmp3 = extractvalue %struct.__neon_int16x8x2_t %tmp2, 0 ; <<8 x i16>> [#uses=1]
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%tmp4 = extractvalue %struct.__neon_int16x8x2_t %tmp2, 1 ; <<8 x i16>> [#uses=1]
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%tmp5 = add <8 x i16> %tmp3, %tmp4 ; <<8 x i16>> [#uses=1]
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ret <8 x i16> %tmp5
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}
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declare <8 x i16> @llvm.arm.neon.vld1.v8i16(i8*) nounwind readonly
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declare <4 x i32> @llvm.arm.neon.vmovls.v4i32(<4 x i16>) nounwind readnone
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declare <4 x i16> @llvm.arm.neon.vshiftn.v4i16(<4 x i32>, <4 x i32>) nounwind readnone
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declare void @llvm.arm.neon.vst1.v8i16(i8*, <8 x i16>) nounwind
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declare void @llvm.arm.neon.vst3.v8i8(i8*, <8 x i8>, <8 x i8>, <8 x i8>) nounwind
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declare %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3.v8i8(i8*) nounwind readonly
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declare %struct.__neon_int32x4x2_t @llvm.arm.neon.vld2.v4i32(i8*) nounwind readonly
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declare %struct.__neon_int16x8x2_t @llvm.arm.neon.vld2lane.v8i16(i8*, <8 x i16>, <8 x i16>, i32) nounwind readonly
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declare void @llvm.arm.neon.vst2.v4i32(i8*, <4 x i32>, <4 x i32>) nounwind
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declare void @llvm.trap() nounwind
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