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Merging r182486:

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r182486 | d0k | 2013-05-22 10:01:12 -0700 (Wed, 22 May 2013) | 3 lines

X86: When expanding PCMPGTQ to PCMPGTD we always want to compare the lower halves as unsigned.

Take #2 on fixing PR15977.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_33@182489 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bill Wendling 2013-05-22 17:23:54 +00:00
parent 5a262f36de
commit 62131ab280
2 changed files with 25 additions and 4 deletions
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15
lib/Target/X86/X86ISelLowering.cpp
View File

@ -9347,12 +9347,19 @@ static SDValue LowerVSETCC(SDValue Op, const X86Subtarget *Subtarget,
Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1); Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
// Since SSE has no unsigned integer comparisons, we need to flip the sign // Since SSE has no unsigned integer comparisons, we need to flip the sign
// bits of the inputs before performing those operations. // bits of the inputs before performing those operations. The lower
// compare is always unsigned.
SDValue SB;
if (FlipSigns) { if (FlipSigns) {
SDValue SB = DAG.getConstant(0x80000000U, MVT::v4i32); SB = DAG.getConstant(0x80000000U, MVT::v4i32);
Op0 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op0, SB); } else {
Op1 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op1, SB); SDValue Sign = DAG.getConstant(0x80000000U, MVT::i32);
SDValue Zero = DAG.getConstant(0x00000000U, MVT::i32);
SB = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
Sign, Zero, Sign, Zero);
} }
Op0 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op0, SB);
Op1 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op1, SB);
// Emulate PCMPGTQ with (hi1 > hi2) | ((hi1 == hi2) & (lo1 > lo2)) // Emulate PCMPGTQ with (hi1 > hi2) | ((hi1 == hi2) & (lo1 > lo2))
SDValue GT = DAG.getNode(X86ISD::PCMPGT, dl, MVT::v4i32, Op0, Op1); SDValue GT = DAG.getNode(X86ISD::PCMPGT, dl, MVT::v4i32, Op0, Op1);

14
test/CodeGen/X86/vec_compare.ll
View File

@ -67,7 +67,15 @@ define <2 x i64> @test6(<2 x i64> %A, <2 x i64> %B) nounwind {
} }
define <2 x i64> @test7(<2 x i64> %A, <2 x i64> %B) nounwind { define <2 x i64> @test7(<2 x i64> %A, <2 x i64> %B) nounwind {
; CHECK: [[CONSTSEG:[A-Z0-9_]*]]:
; CHECK: .long 2147483648
; CHECK-NEXT: .long 0
; CHECK-NEXT: .long 2147483648
; CHECK-NEXT: .long 0
; CHECK: test7: ; CHECK: test7:
; CHECK: movdqa [[CONSTSEG]], [[CONSTREG:%xmm[0-9]*]]
; CHECK: pxor [[CONSTREG]]
; CHECK: pxor [[CONSTREG]]
; CHECK: pcmpgtd %xmm1 ; CHECK: pcmpgtd %xmm1
; CHECK: pshufd $-96 ; CHECK: pshufd $-96
; CHECK: pcmpeqd ; CHECK: pcmpeqd
@ -83,6 +91,8 @@ define <2 x i64> @test7(<2 x i64> %A, <2 x i64> %B) nounwind {
define <2 x i64> @test8(<2 x i64> %A, <2 x i64> %B) nounwind { define <2 x i64> @test8(<2 x i64> %A, <2 x i64> %B) nounwind {
; CHECK: test8: ; CHECK: test8:
; CHECK: pxor
; CHECK: pxor
; CHECK: pcmpgtd %xmm0 ; CHECK: pcmpgtd %xmm0
; CHECK: pshufd $-96 ; CHECK: pshufd $-96
; CHECK: pcmpeqd ; CHECK: pcmpeqd
@ -98,6 +108,8 @@ define <2 x i64> @test8(<2 x i64> %A, <2 x i64> %B) nounwind {
define <2 x i64> @test9(<2 x i64> %A, <2 x i64> %B) nounwind { define <2 x i64> @test9(<2 x i64> %A, <2 x i64> %B) nounwind {
; CHECK: test9: ; CHECK: test9:
; CHECK: pxor
; CHECK: pxor
; CHECK: pcmpgtd %xmm0 ; CHECK: pcmpgtd %xmm0
; CHECK: pshufd $-96 ; CHECK: pshufd $-96
; CHECK: pcmpeqd ; CHECK: pcmpeqd
@ -115,6 +127,8 @@ define <2 x i64> @test9(<2 x i64> %A, <2 x i64> %B) nounwind {
define <2 x i64> @test10(<2 x i64> %A, <2 x i64> %B) nounwind { define <2 x i64> @test10(<2 x i64> %A, <2 x i64> %B) nounwind {
; CHECK: test10: ; CHECK: test10:
; CHECK: pxor
; CHECK: pxor
; CHECK: pcmpgtd %xmm1 ; CHECK: pcmpgtd %xmm1
; CHECK: pshufd $-96 ; CHECK: pshufd $-96
; CHECK: pcmpeqd ; CHECK: pcmpeqd