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Use SmallVectorImpl::iterator/const_iterator instead of SmallVector to avoid specifying the vector size.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185606 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -1484,7 +1484,7 @@ namespace {
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unsigned &PredReg, ARMCC::CondCodes &Pred,
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bool &isT2);
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bool RescheduleOps(MachineBasicBlock *MBB,
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SmallVector<MachineInstr*, 4> &Ops,
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SmallVectorImpl<MachineInstr *> &Ops,
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unsigned Base, bool isLd,
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DenseMap<MachineInstr*, unsigned> &MI2LocMap);
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bool RescheduleLoadStoreInstrs(MachineBasicBlock *MBB);
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@ -1656,7 +1656,7 @@ namespace {
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}
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bool ARMPreAllocLoadStoreOpt::RescheduleOps(MachineBasicBlock *MBB,
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SmallVector<MachineInstr*, 4> &Ops,
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SmallVectorImpl<MachineInstr *> &Ops,
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unsigned Base, bool isLd,
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DenseMap<MachineInstr*, unsigned> &MI2LocMap) {
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bool RetVal = false;
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@ -1894,7 +1894,7 @@ ARMPreAllocLoadStoreOpt::RescheduleLoadStoreInstrs(MachineBasicBlock *MBB) {
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// Re-schedule loads.
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for (unsigned i = 0, e = LdBases.size(); i != e; ++i) {
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unsigned Base = LdBases[i];
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SmallVector<MachineInstr*, 4> &Lds = Base2LdsMap[Base];
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SmallVectorImpl<MachineInstr *> &Lds = Base2LdsMap[Base];
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if (Lds.size() > 1)
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RetVal |= RescheduleOps(MBB, Lds, Base, true, MI2LocMap);
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}
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@ -1902,7 +1902,7 @@ ARMPreAllocLoadStoreOpt::RescheduleLoadStoreInstrs(MachineBasicBlock *MBB) {
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// Re-schedule stores.
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for (unsigned i = 0, e = StBases.size(); i != e; ++i) {
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unsigned Base = StBases[i];
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SmallVector<MachineInstr*, 4> &Sts = Base2StsMap[Base];
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SmallVectorImpl<MachineInstr *> &Sts = Base2StsMap[Base];
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if (Sts.size() > 1)
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RetVal |= RescheduleOps(MBB, Sts, Base, false, MI2LocMap);
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}
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