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Make CVTDQ2PS instruction use SSE2 predicate instead of SSE1. No functional change because there are no patterns in the instructions. Also fix a typo in a comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159087 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -366,7 +366,7 @@ class VPSI<bits<8> o, Format F, dag outs, dag ins, string asm,
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//
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// SDI - SSE2 instructions with XD prefix.
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// SDIi8 - SSE2 instructions with ImmT == Imm8 and XD prefix.
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// SSDI - SSE2 instructions with XD prefix.
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// SSDI - SSE2 instructions with XS prefix.
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// SSDIi8 - SSE2 instructions with ImmT == Imm8 and XS prefix.
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// PDI - SSE2 instructions with TB and OpSize prefixes.
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// PDIi8 - SSE2 instructions with ImmT == Imm8 and TB and OpSize prefixes.
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@ -1418,10 +1418,10 @@ multiclass sse12_cvt_s<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
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multiclass sse12_cvt_p<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
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SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
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string asm, Domain d, OpndItins itins> {
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def rr : PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
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def rr : I<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
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[(set DstRC:$dst, (OpNode SrcRC:$src))],
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itins.rr, d>;
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def rm : PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
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def rm : I<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
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[(set DstRC:$dst, (OpNode (ld_frag addr:$src)))],
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itins.rm, d>;
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}
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@ -1630,11 +1630,13 @@ defm VCVTSS2SI64 : sse12_cvt_s<0x2D, FR32, GR64, undef, f32mem, load,
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"cvtss2si\t{$src, $dst|$dst, $src}",
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SSE_CVT_SS2SI_64>, XS, VEX, VEX_W, VEX_LIG;
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defm VCVTDQ2PS : sse12_cvt_p<0x5B, VR128, VR128, undef, i128mem, load,
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"cvtdq2ps\t{$src, $dst|$dst, $src}",
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SSEPackedSingle, SSE_CVT_PS>, TB, VEX;
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"vcvtdq2ps\t{$src, $dst|$dst, $src}",
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SSEPackedSingle, SSE_CVT_PS>, TB, VEX,
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Requires<[HasAVX]>;
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defm VCVTDQ2PSY : sse12_cvt_p<0x5B, VR256, VR256, undef, i256mem, load,
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"cvtdq2ps\t{$src, $dst|$dst, $src}",
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SSEPackedSingle, SSE_CVT_PS>, TB, VEX;
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"vcvtdq2ps\t{$src, $dst|$dst, $src}",
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SSEPackedSingle, SSE_CVT_PS>, TB, VEX,
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Requires<[HasAVX]>;
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}
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let Pattern = []<dag> in {
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@ -1646,8 +1648,8 @@ defm CVTSS2SI64 : sse12_cvt_s<0x2D, FR32, GR64, undef, f32mem, load /*dummy*/,
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SSE_CVT_SS2SI_64>, XS, REX_W;
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defm CVTDQ2PS : sse12_cvt_p<0x5B, VR128, VR128, undef, i128mem, load /*dummy*/,
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"cvtdq2ps\t{$src, $dst|$dst, $src}",
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SSEPackedSingle, SSE_CVT_PS>,
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TB; /* PD SSE3 form is avaiable */
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SSEPackedSingle, SSE_CVT_PS>, TB,
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Requires<[HasSSE2]>;
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}
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let Predicates = [HasAVX] in {
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