major think-o

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24564 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Andrew Lenharth 2005-12-01 17:48:51 +00:00
parent 6510b22cec
commit 6251b36d88

View File

@ -1538,23 +1538,28 @@ unsigned AlphaISel::SelectExpr(SDOperand N) {
return Result;
case AlphaISD::CVTQT_:
BuildMI(BB, Alpha::CVTQT, 1, Result).addReg(SelectExpr(N.getOperand(0)));
Tmp1 = SelectExpr(N.getOperand(0));
BuildMI(BB, Alpha::CVTQT, 1, Result).addReg(Tmp1);
return Result;
case AlphaISD::CVTQS_:
BuildMI(BB, Alpha::CVTQS, 1, Result).addReg(SelectExpr(N.getOperand(0)));
Tmp1 = SelectExpr(N.getOperand(0));
BuildMI(BB, Alpha::CVTQS, 1, Result).addReg(Tmp1);
return Result;
case AlphaISD::CVTTQ_:
BuildMI(BB, Alpha::CVTTQ, 1, Result).addReg(SelectExpr(N.getOperand(0)));
Tmp1 = SelectExpr(N.getOperand(0));
BuildMI(BB, Alpha::CVTTQ, 1, Result).addReg(Tmp1);
return Result;
case AlphaISD::ITOFT_:
BuildMI(BB, Alpha::ITOFT, 1, Result).addReg(SelectExpr(N.getOperand(0)));
Tmp1 = SelectExpr(N.getOperand(0));
BuildMI(BB, Alpha::ITOFT, 1, Result).addReg(Tmp1);
return Result;
case AlphaISD::FTOIT_:
BuildMI(BB, Alpha::FTOIT, 1, Result).addReg(SelectExpr(N.getOperand(0)));
Tmp1 = SelectExpr(N.getOperand(0));
BuildMI(BB, Alpha::FTOIT, 1, Result).addReg(Tmp1);
return Result;
case ISD::AssertSext: