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https://github.com/c64scene-ar/llvm-6502.git
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Select ADC, SBC, and RSC instead of the ADCS, SBCS, and RSCS when the carry bit def is not used.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74228 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng
parent
0b49c32c56
commit
6267422318
@ -103,6 +103,8 @@ def HasThumb2 : Predicate<"Subtarget->hasThumb2()">;
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def IsARM : Predicate<"!Subtarget->isThumb()">;
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def IsDarwin : Predicate<"Subtarget->isTargetDarwin()">;
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def IsNotDarwin : Predicate<"!Subtarget->isTargetDarwin()">;
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def CarryDefIsUnused : Predicate<"N.getNode()->hasNUsesOfValue(0, 1)">;
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def CarryDefIsUsed : Predicate<"N.getNode()->hasAnyUseOfValue(1)">;
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//===----------------------------------------------------------------------===//
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// ARM Flag Definitions.
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@ -430,19 +432,40 @@ multiclass AI_bin_rrot<bits<8> opcod, string opc, PatFrag opnode> {
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Requires<[IsARM, HasV6]>;
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}
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/// AI1_bin_cs_irs - A binary operation that both uses and defines CPSR. It's
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/// currently not predicable.
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let Defs = [CPSR], Uses = [CPSR] in {
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multiclass AI1_bin_cs_irs<bits<4> opcod, string opc, PatFrag opnode> {
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def ri : AXI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_imm:$b),
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/// AI1_adde_sube_irs - Define instructions and patterns for adde and sube.
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let Uses = [CPSR] in {
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multiclass AI1_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode> {
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def ri : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_imm:$b),
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DPFrm, opc, " $dst, $a, $b",
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[(set GPR:$dst, (opnode GPR:$a, so_imm:$b))]>,
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Requires<[IsARM, CarryDefIsUnused]>;
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def rr : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
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DPFrm, opc, " $dst, $a, $b",
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[(set GPR:$dst, (opnode GPR:$a, GPR:$b))]>,
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Requires<[IsARM, CarryDefIsUnused]>;
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def rs : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_reg:$b),
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DPSoRegFrm, opc, " $dst, $a, $b",
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[(set GPR:$dst, (opnode GPR:$a, so_reg:$b))]>,
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Requires<[IsARM, CarryDefIsUnused]>;
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// Carry setting variants
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def Sri : AXI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_imm:$b),
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DPFrm, !strconcat(opc, "s $dst, $a, $b"),
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[(set GPR:$dst, (opnode GPR:$a, so_imm:$b))]>;
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def rr : AXI1<opcod, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
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[(set GPR:$dst, (opnode GPR:$a, so_imm:$b))]>,
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Requires<[IsARM, CarryDefIsUsed]> {
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let Defs = [CPSR];
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}
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def Srr : AXI1<opcod, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
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DPFrm, !strconcat(opc, "s $dst, $a, $b"),
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[(set GPR:$dst, (opnode GPR:$a, GPR:$b))]>;
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def rs : AXI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_reg:$b),
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[(set GPR:$dst, (opnode GPR:$a, GPR:$b))]>,
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Requires<[IsARM, CarryDefIsUsed]> {
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let Defs = [CPSR];
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}
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def Srs : AXI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_reg:$b),
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DPSoRegFrm, !strconcat(opc, "s $dst, $a, $b"),
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[(set GPR:$dst, (opnode GPR:$a, so_reg:$b))]>;
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[(set GPR:$dst, (opnode GPR:$a, so_reg:$b))]>,
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Requires<[IsARM, CarryDefIsUsed]> {
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let Defs = [CPSR];
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}
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}
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}
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@ -910,11 +933,10 @@ defm ADDS : AI1_bin_s_irs<0b0100, "add",
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defm SUBS : AI1_bin_s_irs<0b0010, "sub",
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BinOpFrag<(subc node:$LHS, node:$RHS)>>;
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// FIXME: Do not allow ADCS / SBCS to be predicated for now.
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defm ADCS : AI1_bin_cs_irs<0b0101, "adc",
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BinOpFrag<(adde node:$LHS, node:$RHS)>>;
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defm SBCS : AI1_bin_cs_irs<0b0110, "sbc",
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BinOpFrag<(sube node:$LHS, node:$RHS)>>;
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defm ADC : AI1_adde_sube_irs<0b0101, "adc",
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BinOpFrag<(adde node:$LHS, node:$RHS)>>;
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defm SBC : AI1_adde_sube_irs<0b0110, "sbc",
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BinOpFrag<(sube node:$LHS, node:$RHS)>>;
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// These don't define reg/reg forms, because they are handled above.
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def RSBri : AsI1<0b0011, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), DPFrm,
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@ -935,14 +957,27 @@ def RSBSrs : AI1<0b0011, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPSoRegFrm,
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[(set GPR:$dst, (subc so_reg:$b, GPR:$a))]>;
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}
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// FIXME: Do not allow RSC to be predicated for now.
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let Uses = [CPSR] in {
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def RSCri : AsI1<0b0111, (outs GPR:$dst), (ins GPR:$a, so_imm:$b),
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DPFrm, "rsc", " $dst, $a, $b",
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[(set GPR:$dst, (sube so_imm:$b, GPR:$a))]>,
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Requires<[IsARM, CarryDefIsUnused]>;
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def RSCrs : AsI1<0b0111, (outs GPR:$dst), (ins GPR:$a, so_reg:$b),
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DPSoRegFrm, "rsc", " $dst, $a, $b",
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[(set GPR:$dst, (sube so_reg:$b, GPR:$a))]>,
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Requires<[IsARM, CarryDefIsUnused]>;
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}
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// FIXME: Allow these to be predicated.
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let Defs = [CPSR], Uses = [CPSR] in {
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def RSCSri : AXI1<0b0111, (outs GPR:$dst), (ins GPR:$a, so_imm:$b),
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DPFrm, "rscs $dst, $a, $b",
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[(set GPR:$dst, (sube so_imm:$b, GPR:$a))]>;
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[(set GPR:$dst, (sube so_imm:$b, GPR:$a))]>,
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Requires<[IsARM, CarryDefIsUnused]>;
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def RSCSrs : AXI1<0b0111, (outs GPR:$dst), (ins GPR:$a, so_reg:$b),
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DPSoRegFrm, "rscs $dst, $a, $b",
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[(set GPR:$dst, (sube so_reg:$b, GPR:$a))]>;
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[(set GPR:$dst, (sube so_reg:$b, GPR:$a))]>,
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Requires<[IsARM, CarryDefIsUnused]>;
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}
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// (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
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@ -223,43 +223,80 @@ multiclass T2I_bin_ii12rs<string opc, PatFrag opnode> {
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[(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>;
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}
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/// T2I_bin_cs_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a
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/// T2I_adde_sube_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a
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/// binary operation that produces a value and use and define the carry bit.
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/// It's not predicable.
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let Defs = [CPSR], Uses = [CPSR] in {
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multiclass T2I_bin_cs_irs<string opc, PatFrag opnode> {
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let Uses = [CPSR] in {
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multiclass T2I_adde_sube_irs<string opc, PatFrag opnode> {
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// shifted imm
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def ri : T2XI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs),
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!strconcat(opc, "s $dst, $lhs, $rhs"),
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[(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>;
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def ri : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs),
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opc, " $dst, $lhs, $rhs",
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[(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>,
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Requires<[IsThumb, HasThumb2, CarryDefIsUnused]>;
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// register
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def rr : T2XI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs),
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!strconcat(opc, "s $dst, $lhs, $rhs"),
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[(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]>;
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def rr : T2sI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs),
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opc, " $dst, $lhs, $rhs",
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[(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]>,
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Requires<[IsThumb, HasThumb2, CarryDefIsUnused]>;
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// shifted register
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def rs : T2XI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs),
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!strconcat(opc, "s $dst, $lhs, $rhs"),
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[(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>;
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def rs : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs),
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opc, "s $dst, $lhs, $rhs",
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[(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>,
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Requires<[IsThumb, HasThumb2, CarryDefIsUnused]>;
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// Carry setting variants
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// shifted imm
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def Sri : T2XI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs),
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!strconcat(opc, "s $dst, $lhs, $rhs"),
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[(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>,
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Requires<[IsThumb, HasThumb2, CarryDefIsUsed]> {
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let Defs = [CPSR];
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}
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// register
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def Srr : T2XI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs),
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!strconcat(opc, "s $dst, $lhs, $rhs"),
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[(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]>,
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Requires<[IsThumb, HasThumb2, CarryDefIsUsed]> {
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let Defs = [CPSR];
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}
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// shifted register
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def Srs : T2XI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs),
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!strconcat(opc, "s $dst, $lhs, $rhs"),
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[(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>,
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Requires<[IsThumb, HasThumb2, CarryDefIsUsed]> {
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let Defs = [CPSR];
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}
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}
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}
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/// T2I_rbin_cs_is - Same as T2I_bin_cs_irs except the order of operands are
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/// T2I_rsc_is - Same as T2I_adde_sube_irs except the order of operands are
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/// reversed. It doesn't define the 'rr' form since it's handled by its
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/// T2I_bin_cs_irs counterpart.
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/// T2I_adde_sube_irs counterpart.
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let Defs = [CPSR], Uses = [CPSR] in {
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multiclass T2I_rbin_cs_is<string opc, PatFrag opnode> {
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multiclass T2I_rsc_is<string opc, PatFrag opnode> {
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// shifted imm
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def ri : T2XI<(outs GPR:$dst), (ins GPR:$rhs, t2_so_imm:$lhs),
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!strconcat(opc, "s $dst, $rhs, $lhs"),
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[(set GPR:$dst, (opnode t2_so_imm:$lhs, GPR:$rhs))]>;
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// register
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def rr : T2XI<(outs GPR:$dst), (ins GPR:$rhs, GPR:$lhs),
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!strconcat(opc, "s $dst, $rhs, $lhs"),
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[(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]>;
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def ri : T2sI<(outs GPR:$dst), (ins GPR:$rhs, t2_so_imm:$lhs),
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opc, " $dst, $rhs, $lhs",
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[(set GPR:$dst, (opnode t2_so_imm:$lhs, GPR:$rhs))]>,
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Requires<[IsThumb, HasThumb2, CarryDefIsUnused]>;
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// shifted register
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def rs : T2XI<(outs GPR:$dst), (ins GPR:$rhs, t2_so_reg:$lhs),
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def rs : T2sI<(outs GPR:$dst), (ins GPR:$rhs, t2_so_reg:$lhs),
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opc, " $dst, $rhs, $lhs",
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[(set GPR:$dst, (opnode t2_so_reg:$lhs, GPR:$rhs))]>,
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Requires<[IsThumb, HasThumb2, CarryDefIsUnused]>;
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// shifted imm
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def Sri : T2XI<(outs GPR:$dst), (ins GPR:$rhs, t2_so_imm:$lhs),
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!strconcat(opc, "s $dst, $rhs, $lhs"),
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[(set GPR:$dst, (opnode t2_so_reg:$lhs, GPR:$rhs))]>;
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[(set GPR:$dst, (opnode t2_so_imm:$lhs, GPR:$rhs))]>,
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Requires<[IsThumb, HasThumb2, CarryDefIsUsed]> {
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let Defs = [CPSR];
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}
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// shifted register
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def Srs : T2XI<(outs GPR:$dst), (ins GPR:$rhs, t2_so_reg:$lhs),
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!strconcat(opc, "s $dst, $rhs, $lhs"),
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[(set GPR:$dst, (opnode t2_so_reg:$lhs, GPR:$rhs))]>,
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Requires<[IsThumb, HasThumb2, CarryDefIsUsed]> {
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let Defs = [CPSR];
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}
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}
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}
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@ -385,14 +422,13 @@ defm t2SUB : T2I_bin_ii12rs<"sub", BinOpFrag<(sub node:$LHS, node:$RHS)>>;
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defm t2ADDS : T2I_bin_s_irs <"add", BinOpFrag<(addc node:$LHS, node:$RHS)>>;
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defm t2SUBS : T2I_bin_s_irs <"sub", BinOpFrag<(subc node:$LHS, node:$RHS)>>;
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// FIXME: predication support
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defm t2ADC : T2I_bin_cs_irs<"adc", BinOpFrag<(adde node:$LHS, node:$RHS)>>;
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defm t2SBC : T2I_bin_cs_irs<"sbc", BinOpFrag<(sube node:$LHS, node:$RHS)>>;
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defm t2ADC : T2I_adde_sube_irs<"adc", BinOpFrag<(adde node:$LHS, node:$RHS)>>;
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defm t2SBC : T2I_adde_sube_irs<"sbc", BinOpFrag<(sube node:$LHS, node:$RHS)>>;
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// RSB, RSC
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defm t2RSB : T2I_rbin_is <"rsb", BinOpFrag<(sub node:$LHS, node:$RHS)>>;
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defm t2RSBS : T2I_rbin_s_is <"rsb", BinOpFrag<(subc node:$LHS, node:$RHS)>>;
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defm t2RSC : T2I_rbin_cs_is<"rsc", BinOpFrag<(sube node:$LHS, node:$RHS)>>;
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defm t2RSC : T2I_rsc_is <"rsc", BinOpFrag<(sube node:$LHS, node:$RHS)>>;
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// (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
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def : Thumb2Pat<(add GPR:$src, t2_so_imm_neg:$imm),
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@ -1,6 +1,6 @@
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; RUN: llvm-as < %s | llc -march=arm | grep "subs r" | count 2
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; RUN: llvm-as < %s | llc -march=arm | grep adc
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; RUN: llvm-as < %s | llc -march=arm | grep sbc
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; RUN: llvm-as < %s | llc -march=arm | grep "adc r"
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; RUN: llvm-as < %s | llc -march=arm | grep "sbc r" | count 2
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define i64 @f1(i64 %a, i64 %b) {
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entry:
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@ -1,6 +1,6 @@
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; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep "subs r" | count 2
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; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep adc
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; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep sbc
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; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep "adc r"
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; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep "sbc r" | count 2
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define i64 @f1(i64 %a, i64 %b) {
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entry:
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