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[mips][microMIPS] Implement SLL and NOP instructions
http://reviews.llvm.org/D10474 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241150 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -272,3 +272,18 @@ class EIDI_MMR6_ENC<string instr_asm, bits<10> funct> : MMR6Arch<instr_asm> {
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let Inst{15-6} = funct;
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let Inst{5-0} = 0x3c;
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}
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class SHIFT_MMR6_ENC<string instr_asm, bits<10> funct, bit rotate> : MMR6Arch<instr_asm> {
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bits<5> rd;
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bits<5> rt;
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bits<5> shamt;
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bits<32> Inst;
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let Inst{31-26} = 0;
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let Inst{25-21} = rd;
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let Inst{20-16} = rt;
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let Inst{15-11} = shamt;
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let Inst{10} = rotate;
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let Inst{9-0} = funct;
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}
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@ -63,6 +63,7 @@ class SEB_MMR6_ENC : SIGN_EXTEND_FM_MMR6<"seb", 0b0010101100>;
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class SEH_MMR6_ENC : SIGN_EXTEND_FM_MMR6<"seh", 0b0011101100>;
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class SELEQZ_MMR6_ENC : POOL32A_FM_MMR6<0b0101000000>;
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class SELNEZ_MMR6_ENC : POOL32A_FM_MMR6<0b0110000000>;
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class SLL_MMR6_ENC : SHIFT_MMR6_ENC<"sll", 0x00, 0b0>;
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class SUB_MMR6_ENC : ARITH_FM_MMR6<"sub", 0x190>;
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class SUBU_MMR6_ENC : ARITH_FM_MMR6<"subu", 0x1d0>;
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class XOR_MMR6_ENC : ARITH_FM_MMR6<"xor", 0x310>;
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@ -263,6 +264,7 @@ class SELEQNE_Z_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd>
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class SELEQZ_MMR6_DESC : SELEQNE_Z_MMR6_DESC_BASE<"seleqz", GPR32Opnd>;
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class SELNEZ_MMR6_DESC : SELEQNE_Z_MMR6_DESC_BASE<"selnez", GPR32Opnd>;
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class SLL_MMR6_DESC : shift_rotate_imm<"sll", uimm5, GPR32Opnd, II_SLL>;
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class DIV_MMR6_DESC : ArithLogicR<"div", GPR32Opnd>;
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class DIVU_MMR6_DESC : ArithLogicR<"divu", GPR32Opnd>;
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class MOD_MMR6_DESC : ArithLogicR<"mod", GPR32Opnd>;
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@ -341,6 +343,7 @@ def SELEQZ_MMR6 : R6MMR6Rel, SELEQZ_MMR6_ENC, SELEQZ_MMR6_DESC,
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ISA_MICROMIPS32R6;
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def SELNEZ_MMR6 : R6MMR6Rel, SELNEZ_MMR6_ENC, SELNEZ_MMR6_DESC,
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ISA_MICROMIPS32R6;
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def SLL_MMR6 : StdMMR6Rel, SLL_MMR6_DESC, SLL_MMR6_ENC, ISA_MICROMIPS32R6;
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def SUB_MMR6 : StdMMR6Rel, SUB_MMR6_DESC, SUB_MMR6_ENC, ISA_MICROMIPS32R6;
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def SUBU_MMR6 : StdMMR6Rel, SUBU_MMR6_DESC, SUBU_MMR6_ENC, ISA_MICROMIPS32R6;
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def XOR_MMR6 : StdMMR6Rel, XOR_MMR6_DESC, XOR_MMR6_ENC, ISA_MICROMIPS32R6;
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@ -354,3 +357,4 @@ def XORI_MMR6 : StdMMR6Rel, XORI_MMR6_DESC, XORI_MMR6_ENC, ISA_MICROMIPS32R6;
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//===----------------------------------------------------------------------===//
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def : MipsInstAlias<"ei", (EI_MMR6 ZERO), 1>, ISA_MICROMIPS32R6;
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def : MipsInstAlias<"nop", (SLL_MMR6 ZERO, ZERO, 0), 1>, ISA_MICROMIPS32R6;
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@ -1611,7 +1611,9 @@ def : MipsInstAlias<"or $rs, $rt, $imm",
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(ORi GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>;
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def : MipsInstAlias<"or $rs, $imm",
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(ORi GPR32Opnd:$rs, GPR32Opnd:$rs, uimm16:$imm), 0>;
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let AdditionalPredicates = [NotInMicroMips] in {
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def : MipsInstAlias<"nop", (SLL ZERO, ZERO, 0), 1>;
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}
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def : MipsInstAlias<"mfc0 $rt, $rd", (MFC0 GPR32Opnd:$rt, COP0Opnd:$rd, 0), 0>;
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def : MipsInstAlias<"mtc0 $rt, $rd", (MTC0 COP0Opnd:$rd, GPR32Opnd:$rt, 0), 0>;
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def : MipsInstAlias<"mfc2 $rt, $rd", (MFC2 GPR32Opnd:$rt, COP2Opnd:$rd, 0), 0>;
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@ -84,6 +84,8 @@
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0x00 0xa4,0x18,0xd8 # CHECK: muhu $3, $4, $5
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0x00 0x00 0x00 0x00 # CHECK: nop
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0x00 0xa4 0x1a 0xd0 # CHECK: nor $3, $4, $5
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0x00,0xa4,0x1a,0x90 # CHECK: or $3, $4, $5
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@ -96,6 +98,8 @@
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0x00 0x83 0x11 0x80 # CHECK: selnez $2, $3, $4
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0x00 0x83 0x38 0x00 # CHECK: sll $4, $3, 7
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0x00 0xa4 0x19 0x90 # CHECK: sub $3, $4, $5
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0x00 0xa4 0x19 0xd0 # CHECK: subu $3, $4, $5
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@ -44,6 +44,7 @@
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muh $3, $4, $5 # CHECK muh $3, $4, $5 # encoding: [0x00,0xa4,0x18,0x58]
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mulu $3, $4, $5 # CHECK mulu $3, $4, $5 # encoding: [0x00,0xa4,0x18,0x98]
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muhu $3, $4, $5 # CHECK muhu $3, $4, $5 # encoding: [0x00,0xa4,0x18,0xd8]
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nop # CHECK: nop # encoding: [0x00,0x00,0x00,0x00]
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nor $3, $4, $5 # CHECK: nor $3, $4, $5 # encoding: [0x00,0xa4,0x1a,0xd0]
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or $3, $4, $5 # CHECK: or $3, $4, $5 # encoding: [0x00,0xa4,0x1a,0x90]
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ori $3, $4, 1234 # CHECK: ori $3, $4, 1234 # encoding: [0x50,0x64,0x04,0xd2]
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@ -52,6 +53,7 @@
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seh $3, $4 # CHECK: seh $3, $4 # encoding: [0x00,0x64,0x3b,0x3c]
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seleqz $2,$3,$4 # CHECK: seleqz $2, $3, $4 # encoding: [0x00,0x83,0x11,0x40]
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selnez $2,$3,$4 # CHECK: selnez $2, $3, $4 # encoding: [0x00,0x83,0x11,0x80]
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sll $4, $3, 7 # CHECK: sll $4, $3, 7 # encoding: [0x00,0x83,0x38,0x00]
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sub $3, $4, $5 # CHECK: sub $3, $4, $5 # encoding: [0x00,0xa4,0x19,0x90]
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subu $3, $4, $5 # CHECK: subu $3, $4, $5 # encoding: [0x00,0xa4,0x19,0xd0]
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xor $3, $4, $5 # CHECK: xor $3, $4, $5 # encoding: [0x00,0xa4,0x1b,0x10]
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