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R600: Increase number of ArrayBase Reg to 32

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Reviewed-by: Tom Stellard <thomas.stellard at amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175443 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Vincent Lejeune 2013-02-18 13:48:09 +00:00
parent 605ff6655b
commit 628f6d5820
1 changed files with 2 additions and 2 deletions
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4
lib/Target/R600/R600RegisterInfo.td
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@ -44,7 +44,7 @@ foreach Index = 0-127 in {
}
// Array Base Register holding input in FS
foreach Index = 448-464 in {
foreach Index = 448-480 in {
def ArrayBase#Index : R600Reg<"ARRAY_BASE", Index>;
}
@ -66,7 +66,7 @@ def PRED_SEL_ONE : R600Reg<"Pred_sel_one", 3>;
def AR_X : R600Reg<"AR.x", 0>;
def R600_ArrayBase : RegisterClass <"AMDGPU", [f32, i32], 32,
(add (sequence "ArrayBase%u", 448, 464))>;
(add (sequence "ArrayBase%u", 448, 480))>;
// special registers for ALU src operands
// const buffer reference, SRCx_SEL contains index
def ALU_CONST : R600Reg<"CBuf", 0>;