Add a target hook to add pre- post-regalloc scheduling passes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83144 91177308-0d34-0410-b5e6-96231b3b80d8

lib/CodeGen/LLVMTargetMachine.cpp

@@ -317,6 +317,10 @@ bool LLVMTargetMachine::addCommonCodeGenPasses(PassManagerBase &PM,
   PM.add(createPrologEpilogCodeInserter());
   printAndVerify(PM);
 
+  // Run pre-sched2 passes.
+  if (addPreSched2(PM, OptLevel))
+    printAndVerify(PM);
+
   // Second pass scheduler.
   if (OptLevel != CodeGenOpt::None) {
     PM.add(createPostRAScheduler());