6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-07-22 09:29:31 +00:00
Code Issues Projects Releases Wiki Activity

Test revert 95050; there's a good chance it's causing

Browse Source 
buildbot failure.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95103 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Dale Johannesen 2010-02-02 18:52:56 +00:00
parent 0823d2a654
commit 62a04136d5
3 changed files with 2 additions and 18 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

14
lib/CodeGen/RegAllocLocal.cpp
View File

@ -764,11 +764,8 @@ void RALocal::AllocateBasicBlock(MachineBasicBlock &MBB) {
// Determine whether this is a copy instruction. The cases where the
// source or destination are phys regs are handled specially.
unsigned SrcCopyReg, DstCopyReg, SrcCopySubReg, DstCopySubReg;
unsigned SrcCopyPhysReg = 0U;
bool isCopy = TII->isMoveInstr(*MI, SrcCopyReg, DstCopyReg,
SrcCopySubReg, DstCopySubReg);
if (isCopy && TargetRegisterInfo::isVirtualRegister(SrcCopyReg))
SrcCopyPhysReg = getVirt2PhysRegMapSlot(SrcCopyReg);
// Loop over the implicit uses, making sure that they are at the head of the
// use order list, so they don't get reallocated.
@ -980,24 +977,13 @@ void RALocal::AllocateBasicBlock(MachineBasicBlock &MBB) {
// If DestVirtReg already has a value, use it.
if (!(DestPhysReg = getVirt2PhysRegMapSlot(DestVirtReg))) {
// If this is a copy try to reuse the input as the output;
// that will make the copy go away.
// If this is a copy, the source reg is a phys reg, and
// that reg is available, use that phys reg for DestPhysReg.
// If this is a copy, the source reg is a virtual reg, and
// the phys reg that was assigned to that virtual reg is now
// available, use that phys reg for DestPhysReg. (If it's now
// available that means this was the last use of the source.)
if (isCopy &&
TargetRegisterInfo::isPhysicalRegister(SrcCopyReg) &&
isPhysRegAvailable(SrcCopyReg)) {
DestPhysReg = SrcCopyReg;
assignVirtToPhysReg(DestVirtReg, DestPhysReg);
} else if (isCopy &&
TargetRegisterInfo::isVirtualRegister(SrcCopyReg) &&
SrcCopyPhysReg && isPhysRegAvailable(SrcCopyPhysReg)) {
DestPhysReg = SrcCopyPhysReg;
assignVirtToPhysReg(DestVirtReg, DestPhysReg);
} else
DestPhysReg = getReg(MBB, MI, DestVirtReg);
}

4
test/CodeGen/PowerPC/2007-04-30-InlineAsmEarlyClobber.ll
View File

@ -1,7 +1,7 @@
; RUN: llc < %s | grep {subfc r3,r5,r4}
; RUN: llc < %s | grep {subfze r4,r2}
; RUN: llc < %s -regalloc=local | grep {subfc r2,r5,r4}
; RUN: llc < %s -regalloc=local | grep {subfze r3,r3}
; RUN: llc < %s -regalloc=local | grep {subfc r5,r4,r3}
; RUN: llc < %s -regalloc=local | grep {subfze r2,r2}
; The first argument of subfc must not be the same as any other register.
; PR1357

2
test/CodeGen/X86/phys-reg-local-regalloc.ll
View File

@ -1,6 +1,4 @@
; RUN: llc < %s -march=x86 -mtriple=i386-apple-darwin9 -regalloc=local | FileCheck %s
; RUN: llc -O0 < %s -march=x86 -mtriple=i386-apple-darwin9 -regalloc=local | FileCheck %s
; CHECKed instructions should be the same with or without -O0.
@.str = private constant [12 x i8] c"x + y = %i\0A\00", align 1 ; <[12 x i8]*> [#uses=1]