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Fix PR123
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@10069 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -1375,7 +1375,7 @@ void ISel::emitDivRemOperation(MachineBasicBlock *BB,
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switch (Class) {
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case cFP: // Floating point divide
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if (isDiv) {
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BuildMI(BB, X86::FpDIV, 2, ResultReg).addReg(Op0Reg).addReg(Op1Reg);
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BMI(BB, IP, X86::FpDIV, 2, ResultReg).addReg(Op0Reg).addReg(Op1Reg);
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} else { // Floating point remainder...
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MachineInstr *TheCall =
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BuildMI(X86::CALLpcrel32, 1).addExternalSymbol("fmod", true);
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@ -1420,26 +1420,26 @@ void ISel::emitDivRemOperation(MachineBasicBlock *BB,
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unsigned ExtReg = ExtRegs[Class];
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// Put the first operand into one of the A registers...
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BuildMI(BB, MovOpcode[Class], 1, Reg).addReg(Op0Reg);
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BMI(BB, IP, MovOpcode[Class], 1, Reg).addReg(Op0Reg);
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if (isSigned) {
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// Emit a sign extension instruction...
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unsigned ShiftResult = makeAnotherReg(Ty);
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BuildMI(BB, SarOpcode[Class], 2, ShiftResult).addReg(Op0Reg).addZImm(31);
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BuildMI(BB, MovOpcode[Class], 1, ExtReg).addReg(ShiftResult);
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BMI(BB, IP, SarOpcode[Class], 2, ShiftResult).addReg(Op0Reg).addZImm(31);
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BMI(BB, IP, MovOpcode[Class], 1, ExtReg).addReg(ShiftResult);
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} else {
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// If unsigned, emit a zeroing instruction... (reg = xor reg, reg)
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BuildMI(BB, ClrOpcode[Class], 2, ExtReg).addReg(ExtReg).addReg(ExtReg);
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BMI(BB, IP, ClrOpcode[Class], 2, ExtReg).addReg(ExtReg).addReg(ExtReg);
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}
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// Emit the appropriate divide or remainder instruction...
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BuildMI(BB, DivOpcode[isSigned][Class], 1).addReg(Op1Reg);
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BMI(BB, IP, DivOpcode[isSigned][Class], 1).addReg(Op1Reg);
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// Figure out which register we want to pick the result out of...
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unsigned DestReg = isDiv ? Reg : ExtReg;
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// Put the result into the destination register...
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BuildMI(BB, MovOpcode[Class], 1, ResultReg).addReg(DestReg);
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BMI(BB, IP, MovOpcode[Class], 1, ResultReg).addReg(DestReg);
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}
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@ -1375,7 +1375,7 @@ void ISel::emitDivRemOperation(MachineBasicBlock *BB,
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switch (Class) {
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case cFP: // Floating point divide
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if (isDiv) {
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BuildMI(BB, X86::FpDIV, 2, ResultReg).addReg(Op0Reg).addReg(Op1Reg);
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BMI(BB, IP, X86::FpDIV, 2, ResultReg).addReg(Op0Reg).addReg(Op1Reg);
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} else { // Floating point remainder...
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MachineInstr *TheCall =
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BuildMI(X86::CALLpcrel32, 1).addExternalSymbol("fmod", true);
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@ -1420,26 +1420,26 @@ void ISel::emitDivRemOperation(MachineBasicBlock *BB,
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unsigned ExtReg = ExtRegs[Class];
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// Put the first operand into one of the A registers...
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BuildMI(BB, MovOpcode[Class], 1, Reg).addReg(Op0Reg);
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BMI(BB, IP, MovOpcode[Class], 1, Reg).addReg(Op0Reg);
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if (isSigned) {
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// Emit a sign extension instruction...
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unsigned ShiftResult = makeAnotherReg(Ty);
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BuildMI(BB, SarOpcode[Class], 2, ShiftResult).addReg(Op0Reg).addZImm(31);
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BuildMI(BB, MovOpcode[Class], 1, ExtReg).addReg(ShiftResult);
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BMI(BB, IP, SarOpcode[Class], 2, ShiftResult).addReg(Op0Reg).addZImm(31);
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BMI(BB, IP, MovOpcode[Class], 1, ExtReg).addReg(ShiftResult);
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} else {
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// If unsigned, emit a zeroing instruction... (reg = xor reg, reg)
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BuildMI(BB, ClrOpcode[Class], 2, ExtReg).addReg(ExtReg).addReg(ExtReg);
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BMI(BB, IP, ClrOpcode[Class], 2, ExtReg).addReg(ExtReg).addReg(ExtReg);
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}
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// Emit the appropriate divide or remainder instruction...
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BuildMI(BB, DivOpcode[isSigned][Class], 1).addReg(Op1Reg);
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BMI(BB, IP, DivOpcode[isSigned][Class], 1).addReg(Op1Reg);
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// Figure out which register we want to pick the result out of...
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unsigned DestReg = isDiv ? Reg : ExtReg;
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// Put the result into the destination register...
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BuildMI(BB, MovOpcode[Class], 1, ResultReg).addReg(DestReg);
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BMI(BB, IP, MovOpcode[Class], 1, ResultReg).addReg(DestReg);
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}
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