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[ARM64] MOVK with sf=0 and hw<1>=1 is unallocated. Shift amount for ADD/SUB instructions is unallocated if shift > 4.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205859 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -906,6 +906,8 @@ static DecodeStatus DecodeMoveImmInstruction(llvm::MCInst &Inst, uint32_t insn,
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case ARM64::MOVZWi:
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case ARM64::MOVNWi:
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case ARM64::MOVKWi:
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if (shift & (1U << 5))
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return Fail;
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DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder);
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break;
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case ARM64::MOVZXi:
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@ -1339,6 +1341,10 @@ static DecodeStatus DecodeAddSubERegInstruction(llvm::MCInst &Inst,
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unsigned Rm = fieldFromInstruction(insn, 16, 5);
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unsigned extend = fieldFromInstruction(insn, 10, 6);
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unsigned shift = extend & 0x7;
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if (shift > 4)
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return Fail;
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switch (Inst.getOpcode()) {
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default:
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return Fail;
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@ -2,6 +2,15 @@
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# LDR/STR: undefined if option field is 10x or 00x.
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# RUN: echo "0x00 0x08 0x20 0xf8" | llvm-mc -triple arm64 -disassemble 2>&1 | FileCheck %s
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# RUN: echo "0x00 0x88 0x00 0xf8" | llvm-mc -triple arm64 -disassemble 2>&1 | FileCheck %s
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# RUN: echo "0x00 0x88 0x20 0xf8" | llvm-mc -triple arm64 -disassemble 2>&1 | FileCheck %s
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# Instructions notionally in the add/sub (extended register) sheet, but with
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# invalid shift amount or "opt" field.
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# RUN: echo "0x00 0x10 0xa0 0x0b" | llvm-mc -triple=arm64 -disassemble 2>&1 | FileCheck %s
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# RUN: echo "0x00 0x10 0x60 0x0b" | llvm-mc -triple=arm64 -disassemble 2>&1 | FileCheck %s
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# RUN: echo "0x00 0x14 0x20 0x0b" | llvm-mc -triple=arm64 -disassemble 2>&1 | FileCheck %s
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# MOVK with sf == 0 and hw<1> == 1 is unallocated.
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# RUN: echo "0x00 0x00 0xc0 0x72" | llvm-mc -triple=arm64 -disassemble 2>&1 | FileCheck %s
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# CHECK: invalid instruction encoding
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