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AArch64: use RegisterOperand for NEON registers.

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Previously we modelled VPR128 and VPR64 as essentially identical
register-classes containing V0-V31 (which had Q0-Q31 as "sub_alias"
sub-registers). This model is starting to cause significant problems
for code generation, particularly writing EXTRACT/INSERT_SUBREG
patterns for converting between the two.

The change here switches to classifying VPR64 & VPR128 as
RegisterOperands, which are essentially aliases for RegisterClasses
with different parsing and printing behaviour. This fits almost
exactly with their real status (VPR128 == FPR128 printed strangely,
VPR64 == FPR64 printed strangely).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190665 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Tim Northover
2013-09-13 07:26:52 +00:00
parent dc6fc4fa1f
commit 630c5e06d6
11 changed files with 238 additions and 274 deletions
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7
test/MC/Disassembler/AArch64/neon-instructions.txt
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@@ -131,8 +131,11 @@
#------------------------------------------------------------------------------
# Vector Move - register
#------------------------------------------------------------------------------
# CHECK: mov v1.16b, v15.16b
# CHECK: mov v25.8b, v4.8b
# FIXME: these should print as "mov", but TableGen can't handle it.
# CHECK: orr v1.16b, v15.16b, v15.16b
# CHECK: orr v25.8b, v4.8b, v4.8b
0xe1 0x1d 0xaf 0x4e
0x99 0x1c 0xa4 0x0e