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Correct NEON encodings for vshrn, vrshl, vrshr, vrshrn.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117402 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Owen Anderson
parent
8ac98cb665
commit
632c235a31
@ -3267,12 +3267,12 @@ defm VSHRN : N2VNSh_HSD<0,1,0b1000,0,0,1, IIC_VSHLiD, "vshrn", "i",
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NEONvshrn>;
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// VRSHL : Vector Rounding Shift
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defm VRSHLs : N3VInt_QHSD<0, 0, 0b0101, 0, N3RegVShFrm,
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defm VRSHLs : N3VInt_QHSDSh<0, 0, 0b0101, 0, N3RegVShFrm,
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IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
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"vrshl", "s", int_arm_neon_vrshifts, 0>;
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defm VRSHLu : N3VInt_QHSD<1, 0, 0b0101, 0, N3RegVShFrm,
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"vrshl", "s", int_arm_neon_vrshifts>;
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defm VRSHLu : N3VInt_QHSDSh<1, 0, 0b0101, 0, N3RegVShFrm,
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IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
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"vrshl", "u", int_arm_neon_vrshiftu, 0>;
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"vrshl", "u", int_arm_neon_vrshiftu>;
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// VRSHR : Vector Rounding Shift Right
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defm VRSHRs : N2VSh_QHSD<0,1,0b0010,1, IIC_VSHLi4D, "vrshr", "s", NEONvrshrs,
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N2RegVShRFrm>;
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@ -345,3 +345,351 @@ define <2 x i64> @vshlli_2xi32(<2 x i32>* %A) nounwind {
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%tmp2 = call <2 x i64> @llvm.arm.neon.vshiftls.v2i64(<2 x i32> %tmp1, <2 x i32> < i32 32, i32 32 >)
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ret <2 x i64> %tmp2
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}
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declare <8 x i8> @llvm.arm.neon.vshiftn.v8i8(<8 x i16>, <8 x i16>) nounwind readnone
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declare <4 x i16> @llvm.arm.neon.vshiftn.v4i16(<4 x i32>, <4 x i32>) nounwind readnone
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declare <2 x i32> @llvm.arm.neon.vshiftn.v2i32(<2 x i64>, <2 x i64>) nounwind readnone
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; CHECK: vshrns_8xi16
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define <8 x i8> @vshrns_8xi16(<8 x i16>* %A) nounwind {
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%tmp1 = load <8 x i16>* %A
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; CHECK: vshrn.i16 d16, q8, #8 @ encoding: [0x30,0x08,0xc8,0xf2]
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%tmp2 = call <8 x i8> @llvm.arm.neon.vshiftn.v8i8(<8 x i16> %tmp1, <8 x i16> < i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8 >)
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ret <8 x i8> %tmp2
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}
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; CHECK: vshrns_4xi32
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define <4 x i16> @vshrns_4xi32(<4 x i32>* %A) nounwind {
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%tmp1 = load <4 x i32>* %A
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; CHECK: vshrn.i32 d16, q8, #16 @ encoding: [0x30,0x08,0xd0,0xf2]
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%tmp2 = call <4 x i16> @llvm.arm.neon.vshiftn.v4i16(<4 x i32> %tmp1, <4 x i32> < i32 -16, i32 -16, i32 -16, i32 -16 >)
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ret <4 x i16> %tmp2
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}
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; CHECK: vshrns_2xi64
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define <2 x i32> @vshrns_2xi64(<2 x i64>* %A) nounwind {
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%tmp1 = load <2 x i64>* %A
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; CHECK: vshrn.i64 d16, q8, #32 @ encoding: [0x30,0x08,0xe0,0xf2]
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%tmp2 = call <2 x i32> @llvm.arm.neon.vshiftn.v2i32(<2 x i64> %tmp1, <2 x i64> < i64 -32, i64 -32 >)
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ret <2 x i32> %tmp2
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}
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declare <8 x i8> @llvm.arm.neon.vrshifts.v8i8(<8 x i8>, <8 x i8>) nounwind readnone
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declare <4 x i16> @llvm.arm.neon.vrshifts.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
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declare <2 x i32> @llvm.arm.neon.vrshifts.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
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declare <1 x i64> @llvm.arm.neon.vrshifts.v1i64(<1 x i64>, <1 x i64>) nounwind readnone
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; CHECK: vrshls_8xi8
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define <8 x i8> @vrshls_8xi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
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%tmp1 = load <8 x i8>* %A
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%tmp2 = load <8 x i8>* %B
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; CHECK: vrshl.s8 d16, d16, d17 @ encoding: [0xa0,0x05,0x41,0xf2]
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%tmp3 = call <8 x i8> @llvm.arm.neon.vrshifts.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
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ret <8 x i8> %tmp3
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}
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; CHECK: vrshls_4xi16
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define <4 x i16> @vrshls_4xi16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
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%tmp1 = load <4 x i16>* %A
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%tmp2 = load <4 x i16>* %B
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; CHECK: vrshl.s16 d16, d16, d17 @ encoding: [0xa0,0x05,0x51,0xf2]
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%tmp3 = call <4 x i16> @llvm.arm.neon.vrshifts.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
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ret <4 x i16> %tmp3
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}
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; CHECK: vrshls_2xi32
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define <2 x i32> @vrshls_2xi32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
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%tmp1 = load <2 x i32>* %A
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%tmp2 = load <2 x i32>* %B
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; CHECK: vrshl.s32 d16, d16, d17 @ encoding: [0xa0,0x05,0x61,0xf2]
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%tmp3 = call <2 x i32> @llvm.arm.neon.vrshifts.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
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ret <2 x i32> %tmp3
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}
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; CHECK: vrshls_1xi64
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define <1 x i64> @vrshls_1xi64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
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%tmp1 = load <1 x i64>* %A
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%tmp2 = load <1 x i64>* %B
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; CHECK: vrshl.s64 d16, d16, d17 @ encoding: [0xa0,0x05,0x71,0xf2]
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%tmp3 = call <1 x i64> @llvm.arm.neon.vrshifts.v1i64(<1 x i64> %tmp1, <1 x i64> %tmp2)
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ret <1 x i64> %tmp3
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}
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declare <8 x i8> @llvm.arm.neon.vrshiftu.v8i8(<8 x i8>, <8 x i8>) nounwind readnone
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declare <4 x i16> @llvm.arm.neon.vrshiftu.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
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declare <2 x i32> @llvm.arm.neon.vrshiftu.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
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declare <1 x i64> @llvm.arm.neon.vrshiftu.v1i64(<1 x i64>, <1 x i64>) nounwind readnone
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; CHECK: vrshlu_8xi8
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define <8 x i8> @vrshlu_8xi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
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%tmp1 = load <8 x i8>* %A
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%tmp2 = load <8 x i8>* %B
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; CHECK: vrshl.u8 d16, d16, d17 @ encoding: [0xa0,0x05,0x41,0xf3]
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%tmp3 = call <8 x i8> @llvm.arm.neon.vrshiftu.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
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ret <8 x i8> %tmp3
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}
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; CHECK: vrshlu_4xi16
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define <4 x i16> @vrshlu_4xi16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
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%tmp1 = load <4 x i16>* %A
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%tmp2 = load <4 x i16>* %B
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; CHECK: vrshl.u16 d16, d16, d17 @ encoding: [0xa0,0x05,0x51,0xf3]
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%tmp3 = call <4 x i16> @llvm.arm.neon.vrshiftu.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
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ret <4 x i16> %tmp3
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}
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; CHECK: vrshlu_2xi32
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define <2 x i32> @vrshlu_2xi32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
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%tmp1 = load <2 x i32>* %A
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%tmp2 = load <2 x i32>* %B
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; CHECK: vrshl.u32 d16, d16, d17 @ encoding: [0xa0,0x05,0x61,0xf3]
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%tmp3 = call <2 x i32> @llvm.arm.neon.vrshiftu.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
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ret <2 x i32> %tmp3
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}
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; CHECK: vrshlu_1xi64
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define <1 x i64> @vrshlu_1xi64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
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%tmp1 = load <1 x i64>* %A
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%tmp2 = load <1 x i64>* %B
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; CHECK: vrshl.u64 d16, d16, d17 @ encoding: [0xa0,0x05,0x71,0xf3]
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%tmp3 = call <1 x i64> @llvm.arm.neon.vrshiftu.v1i64(<1 x i64> %tmp1, <1 x i64> %tmp2)
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ret <1 x i64> %tmp3
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}
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declare <16 x i8> @llvm.arm.neon.vrshifts.v16i8(<16 x i8>, <16 x i8>) nounwind readnone
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declare <8 x i16> @llvm.arm.neon.vrshifts.v8i16(<8 x i16>, <8 x i16>) nounwind readnone
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declare <4 x i32> @llvm.arm.neon.vrshifts.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
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declare <2 x i64> @llvm.arm.neon.vrshifts.v2i64(<2 x i64>, <2 x i64>) nounwind readnone
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; CHECK: vrshls_16xi8
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define <16 x i8> @vrshls_16xi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
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%tmp1 = load <16 x i8>* %A
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%tmp2 = load <16 x i8>* %B
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; CHECK: vrshl.s8 q8, q8, q9 @ encoding: [0xe0,0x05,0x42,0xf2]
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%tmp3 = call <16 x i8> @llvm.arm.neon.vrshifts.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
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ret <16 x i8> %tmp3
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}
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; CHECK: vrshls_8xi16
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define <8 x i16> @vrshls_8xi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
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%tmp1 = load <8 x i16>* %A
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%tmp2 = load <8 x i16>* %B
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; CHECK: vrshl.s16 q8, q8, q9 @ encoding: [0xe0,0x05,0x52,0xf2]
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%tmp3 = call <8 x i16> @llvm.arm.neon.vrshifts.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
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ret <8 x i16> %tmp3
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}
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; CHECK: vrshls_4xi32
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define <4 x i32> @vrshls_4xi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
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%tmp1 = load <4 x i32>* %A
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%tmp2 = load <4 x i32>* %B
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; CHECK: vrshl.s32 q8, q8, q9 @ encoding: [0xe0,0x05,0x62,0xf2]
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%tmp3 = call <4 x i32> @llvm.arm.neon.vrshifts.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
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ret <4 x i32> %tmp3
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}
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; CHECK: vrshls_2xi64
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define <2 x i64> @vrshls_2xi64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
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%tmp1 = load <2 x i64>* %A
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%tmp2 = load <2 x i64>* %B
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; CHECK: vrshl.s64 q8, q8, q9 @ encoding: [0xe0,0x05,0x72,0xf2]
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%tmp3 = call <2 x i64> @llvm.arm.neon.vrshifts.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2)
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ret <2 x i64> %tmp3
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}
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declare <16 x i8> @llvm.arm.neon.vrshiftu.v16i8(<16 x i8>, <16 x i8>) nounwind readnone
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declare <8 x i16> @llvm.arm.neon.vrshiftu.v8i16(<8 x i16>, <8 x i16>) nounwind readnone
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declare <4 x i32> @llvm.arm.neon.vrshiftu.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
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declare <2 x i64> @llvm.arm.neon.vrshiftu.v2i64(<2 x i64>, <2 x i64>) nounwind readnone
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; CHECK: vrshlu_16xi8
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define <16 x i8> @vrshlu_16xi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
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%tmp1 = load <16 x i8>* %A
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%tmp2 = load <16 x i8>* %B
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; CHECK: vrshl.u8 q8, q8, q9 @ encoding: [0xe0,0x05,0x42,0xf3]
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%tmp3 = call <16 x i8> @llvm.arm.neon.vrshiftu.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
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ret <16 x i8> %tmp3
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}
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; CHECK: vrshlu_8xi16
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define <8 x i16> @vrshlu_8xi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
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%tmp1 = load <8 x i16>* %A
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%tmp2 = load <8 x i16>* %B
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; CHECK: vrshl.u16 q8, q8, q9 @ encoding: [0xe0,0x05,0x52,0xf3]
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%tmp3 = call <8 x i16> @llvm.arm.neon.vrshiftu.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
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ret <8 x i16> %tmp3
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}
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; CHECK: vrshlu_4xi32
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define <4 x i32> @vrshlu_4xi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
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%tmp1 = load <4 x i32>* %A
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%tmp2 = load <4 x i32>* %B
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; CHECK: vrshl.u32 q8, q8, q9 @ encoding: [0xe0,0x05,0x62,0xf3]
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%tmp3 = call <4 x i32> @llvm.arm.neon.vrshiftu.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
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ret <4 x i32> %tmp3
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}
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; CHECK: vrshlu_2xi64
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define <2 x i64> @vrshlu_2xi64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
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%tmp1 = load <2 x i64>* %A
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%tmp2 = load <2 x i64>* %B
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; CHECK: vrshl.u64 q8, q8, q9 @ encoding: [0xe0,0x05,0x72,0xf3]
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%tmp3 = call <2 x i64> @llvm.arm.neon.vrshiftu.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2)
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ret <2 x i64> %tmp3
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}
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; CHECK: vrshrs_8xi8
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define <8 x i8> @vrshrs_8xi8(<8 x i8>* %A) nounwind {
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%tmp1 = load <8 x i8>* %A
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; CHECK: vrshr.s8 d16, d16, #8 @ encoding: [0x30,0x02,0xc8,0xf2]
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%tmp2 = call <8 x i8> @llvm.arm.neon.vrshifts.v8i8(<8 x i8> %tmp1, <8 x i8> < i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8 >)
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ret <8 x i8> %tmp2
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}
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; CHECK: vrshrs_4xi16
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define <4 x i16> @vrshrs_4xi16(<4 x i16>* %A) nounwind {
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%tmp1 = load <4 x i16>* %A
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; CHECK: vrshr.s16 d16, d16, #16 @ encoding: [0x30,0x02,0xd0,0xf2]
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%tmp2 = call <4 x i16> @llvm.arm.neon.vrshifts.v4i16(<4 x i16> %tmp1, <4 x i16> < i16 -16, i16 -16, i16 -16, i16 -16 >)
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ret <4 x i16> %tmp2
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}
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; CHECK: vrshrs_2xi32
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define <2 x i32> @vrshrs_2xi32(<2 x i32>* %A) nounwind {
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%tmp1 = load <2 x i32>* %A
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; CHECK: vrshr.s32 d16, d16, #32 @ encoding: [0x30,0x02,0xe0,0xf2]
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%tmp2 = call <2 x i32> @llvm.arm.neon.vrshifts.v2i32(<2 x i32> %tmp1, <2 x i32> < i32 -32, i32 -32 >)
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ret <2 x i32> %tmp2
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}
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; CHECK: vrshrs_1xi64
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define <1 x i64> @vrshrs_1xi64(<1 x i64>* %A) nounwind {
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%tmp1 = load <1 x i64>* %A
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; CHECK: vrshr.s64 d16, d16, #64 @ encoding: [0xb0,0x02,0xc0,0xf2]
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%tmp2 = call <1 x i64> @llvm.arm.neon.vrshifts.v1i64(<1 x i64> %tmp1, <1 x i64> < i64 -64 >)
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ret <1 x i64> %tmp2
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}
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; CHECK: vrshru_8xi8
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define <8 x i8> @vrshru_8xi8(<8 x i8>* %A) nounwind {
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%tmp1 = load <8 x i8>* %A
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; CHECK: vrshr.u8 d16, d16, #8 @ encoding: [0x30,0x02,0xc8,0xf3]
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%tmp2 = call <8 x i8> @llvm.arm.neon.vrshiftu.v8i8(<8 x i8> %tmp1, <8 x i8> < i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8 >)
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ret <8 x i8> %tmp2
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}
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; CHECK: vrshru_4xi16
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define <4 x i16> @vrshru_4xi16(<4 x i16>* %A) nounwind {
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%tmp1 = load <4 x i16>* %A
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; CHECK: vrshr.u16 d16, d16, #16 @ encoding: [0x30,0x02,0xd0,0xf3]
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%tmp2 = call <4 x i16> @llvm.arm.neon.vrshiftu.v4i16(<4 x i16> %tmp1, <4 x i16> < i16 -16, i16 -16, i16 -16, i16 -16 >)
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ret <4 x i16> %tmp2
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}
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; CHECK: vrshru_2xi32
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define <2 x i32> @vrshru_2xi32(<2 x i32>* %A) nounwind {
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%tmp1 = load <2 x i32>* %A
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; CHECK: vrshr.u32 d16, d16, #32 @ encoding: [0x30,0x02,0xe0,0xf3]
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%tmp2 = call <2 x i32> @llvm.arm.neon.vrshiftu.v2i32(<2 x i32> %tmp1, <2 x i32> < i32 -32, i32 -32 >)
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ret <2 x i32> %tmp2
|
||||
}
|
||||
|
||||
; CHECK: vrshru_1xi64
|
||||
define <1 x i64> @vrshru_1xi64(<1 x i64>* %A) nounwind {
|
||||
%tmp1 = load <1 x i64>* %A
|
||||
; CHECK: vrshr.u64 d16, d16, #64 @ encoding: [0xb0,0x02,0xc0,0xf3]
|
||||
%tmp2 = call <1 x i64> @llvm.arm.neon.vrshiftu.v1i64(<1 x i64> %tmp1, <1 x i64> < i64 -64 >)
|
||||
ret <1 x i64> %tmp2
|
||||
}
|
||||
|
||||
; CHECK: vrshrs_16xi8
|
||||
define <16 x i8> @vrshrs_16xi8(<16 x i8>* %A) nounwind {
|
||||
%tmp1 = load <16 x i8>* %A
|
||||
; CHECK: vrshr.s8 q8, q8, #8 @ encoding: [0x70,0x02,0xc8,0xf2]
|
||||
%tmp2 = call <16 x i8> @llvm.arm.neon.vrshifts.v16i8(<16 x i8> %tmp1, <16 x i8> < i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8 >)
|
||||
ret <16 x i8> %tmp2
|
||||
}
|
||||
|
||||
; CHECK: vrshrs_8xi16
|
||||
define <8 x i16> @vrshrs_8xi16(<8 x i16>* %A) nounwind {
|
||||
%tmp1 = load <8 x i16>* %A
|
||||
; CHECK: vrshr.s16 q8, q8, #16 @ encoding: [0x70,0x02,0xd0,0xf2]
|
||||
%tmp2 = call <8 x i16> @llvm.arm.neon.vrshifts.v8i16(<8 x i16> %tmp1, <8 x i16> < i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16 >)
|
||||
ret <8 x i16> %tmp2
|
||||
}
|
||||
|
||||
; CHECK: vrshrs_4xi32
|
||||
define <4 x i32> @vrshrs_4xi32(<4 x i32>* %A) nounwind {
|
||||
%tmp1 = load <4 x i32>* %A
|
||||
; CHECK: vrshr.s32 q8, q8, #32 @ encoding: [0x70,0x02,0xe0,0xf2]
|
||||
%tmp2 = call <4 x i32> @llvm.arm.neon.vrshifts.v4i32(<4 x i32> %tmp1, <4 x i32> < i32 -32, i32 -32, i32 -32, i32 -32 >)
|
||||
ret <4 x i32> %tmp2
|
||||
}
|
||||
|
||||
; CHECK: vrshrs_2xi64
|
||||
define <2 x i64> @vrshrs_2xi64(<2 x i64>* %A) nounwind {
|
||||
%tmp1 = load <2 x i64>* %A
|
||||
; CHECK: vrshr.s64 q8, q8, #64 @ encoding: [0xf0,0x02,0xc0,0xf2]
|
||||
%tmp2 = call <2 x i64> @llvm.arm.neon.vrshifts.v2i64(<2 x i64> %tmp1, <2 x i64> < i64 -64, i64 -64 >)
|
||||
ret <2 x i64> %tmp2
|
||||
}
|
||||
|
||||
; CHECK: vrshru_16xi8
|
||||
define <16 x i8> @vrshru_16xi8(<16 x i8>* %A) nounwind {
|
||||
%tmp1 = load <16 x i8>* %A
|
||||
; CHECK: vrshr.u8 q8, q8, #8 @ encoding: [0x70,0x02,0xc8,0xf3]
|
||||
%tmp2 = call <16 x i8> @llvm.arm.neon.vrshiftu.v16i8(<16 x i8> %tmp1, <16 x i8> < i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8 >)
|
||||
ret <16 x i8> %tmp2
|
||||
}
|
||||
|
||||
; CHECK: vrshru_8xi16
|
||||
define <8 x i16> @vrshru_8xi16(<8 x i16>* %A) nounwind {
|
||||
%tmp1 = load <8 x i16>* %A
|
||||
; CHECK: vrshr.u16 q8, q8, #16 @ encoding: [0x70,0x02,0xd0,0xf3]
|
||||
%tmp2 = call <8 x i16> @llvm.arm.neon.vrshiftu.v8i16(<8 x i16> %tmp1, <8 x i16> < i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16 >)
|
||||
ret <8 x i16> %tmp2
|
||||
}
|
||||
|
||||
; CHECK: vrshru_4xi32
|
||||
define <4 x i32> @vrshru_4xi32(<4 x i32>* %A) nounwind {
|
||||
%tmp1 = load <4 x i32>* %A
|
||||
; CHECK: vrshr.u32 q8, q8, #32 @ encoding: [0x70,0x02,0xe0,0xf3]
|
||||
%tmp2 = call <4 x i32> @llvm.arm.neon.vrshiftu.v4i32(<4 x i32> %tmp1, <4 x i32> < i32 -32, i32 -32, i32 -32, i32 -32 >)
|
||||
ret <4 x i32> %tmp2
|
||||
}
|
||||
|
||||
; CHECK: vrshru_2xi64
|
||||
define <2 x i64> @vrshru_2xi64(<2 x i64>* %A) nounwind {
|
||||
%tmp1 = load <2 x i64>* %A
|
||||
; CHECK: vrshr.u64 q8, q8, #64 @ encoding: [0xf0,0x02,0xc0,0xf3]
|
||||
%tmp2 = call <2 x i64> @llvm.arm.neon.vrshiftu.v2i64(<2 x i64> %tmp1, <2 x i64> < i64 -64, i64 -64 >)
|
||||
ret <2 x i64> %tmp2
|
||||
}
|
||||
|
||||
declare <8 x i8> @llvm.arm.neon.vrshiftn.v8i8(<8 x i16>, <8 x i16>) nounwind readnone
|
||||
declare <4 x i16> @llvm.arm.neon.vrshiftn.v4i16(<4 x i32>, <4 x i32>) nounwind readnone
|
||||
declare <2 x i32> @llvm.arm.neon.vrshiftn.v2i32(<2 x i64>, <2 x i64>) nounwind readnone
|
||||
|
||||
; CHECK: vrshrns_8xi16
|
||||
define <8 x i8> @vrshrns_8xi16(<8 x i16>* %A) nounwind {
|
||||
%tmp1 = load <8 x i16>* %A
|
||||
; CHECK: vrshrn.i16 d16, q8, #8 @ encoding: [0x70,0x08,0xc8,0xf2]
|
||||
%tmp2 = call <8 x i8> @llvm.arm.neon.vrshiftn.v8i8(<8 x i16> %tmp1, <8 x i16> < i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8 >)
|
||||
ret <8 x i8> %tmp2
|
||||
}
|
||||
|
||||
; CHECK: vrshrns_4xi32
|
||||
define <4 x i16> @vrshrns_4xi32(<4 x i32>* %A) nounwind {
|
||||
%tmp1 = load <4 x i32>* %A
|
||||
; CHECK: vrshrn.i32 d16, q8, #16 @ encoding: [0x70,0x08,0xd0,0xf2]
|
||||
%tmp2 = call <4 x i16> @llvm.arm.neon.vrshiftn.v4i16(<4 x i32> %tmp1, <4 x i32> < i32 -16, i32 -16, i32 -16, i32 -16 >)
|
||||
ret <4 x i16> %tmp2
|
||||
}
|
||||
|
||||
; CHECK: vrshrns_2xi64
|
||||
define <2 x i32> @vrshrns_2xi64(<2 x i64>* %A) nounwind {
|
||||
%tmp1 = load <2 x i64>* %A
|
||||
; CHECK: vrshrn.i64 d16, q8, #32 @ encoding: [0x70,0x08,0xe0,0xf2]
|
||||
%tmp2 = call <2 x i32> @llvm.arm.neon.vrshiftn.v2i32(<2 x i64> %tmp1, <2 x i64> < i64 -32, i64 -32 >)
|
||||
ret <2 x i32> %tmp2
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user